Calcium titanate (CaTiO3) with the general formula for perovskites, ABO3, is of technological importance, particularly with regard to dielectric properties. In this work, CaTiO3 ceramic material was prepared by the conventional solid state reaction method. The dielectric properties, impedance characteristics and modulus behavior of the CaTiO3 ceramic material sintered at 1240 °C were investigated in the frequency range of 10−2-106 Hz and temperature range of 100-250 °C. The XRD analysis of the sintered CaTiO3 shows that it is an orthorhombic structure with lattice parameters a = 5.4398 Å, b = 7.6417 Å, and c = 5.3830 Å. The FESEM micrograph shows a significant difference in grain size distribution ranging from 0.26 to 2.32 μm. The AC conductivity, σAC, is found to increase with increasing temperature within the frequency range of 10−2-106 Hz confirming the hopping of electrons to be the conduction mechanism. Due to the decreasing values of the frequency exponent s with increasing temperature, the results of the σAC are discussed using the correlated barrier height (CBH) model. For dielectric studies, the dielectric constant, ε′ is found to decrease with increasing frequency. In the whole temperature range of 100-250 °C, high and low frequency plateau are observed. Each converges at high frequency (>105 Hz) for all the temperatures. The frequency dependence of loss tangent, tan δ, decreases with rise in temperature, with the loss tangent peak shifting to higher frequency. Due to its dielectric characteristics, it is a suitable candidate for developing a variety of capacitors. For the master modulus plot, the shapes remain unchanged in the temperature range considered. The Cole-Cole plots reveal that two primary relaxation processes exist in the sample for each temperature. The Nyquist plots reveal that at temperatures below 150 °C, a linear response in the imaginary part of the impedance, Z′′, is noticed. At and above 175 °C, the linear response gradually changes to a semicircle arc. The modulus behavior indicates the presence of correlation between the motions of mobile charge carriers. The plots of Arrhenius diagram of relaxation times of loss tangent, τtanδ, and imaginary part of dielectric modulus, τM′′, obey the Arrhenius law, where the activation energies calculated from the slopes are 2.09 and 2.38 eV respectively.

The junctionless nanowire transistor is a promising alternative for a new generation of nanotransistors. In this letter the atomic force microscopy nanolithography with two wet etching processes was implemented to fabricate simple structures as double gate and single gate junctionless silicon nanowire transistor on low doped p-type silicon-on-insulator wafer. The etching process was developed and optimized in the present work compared to our previous works. The output, transfer characteristics and drain conductance of both structures were compared. The trend for both devices found to be the same but differences in subthreshold swing, ‘on/off’ ratio, and threshold voltage were observed. The devices are ‘on’ state when performing as the pinch off devices. The positive gate voltage shows pinch off effect, while the negative gate voltage was unable to make a significant effect on drain current. The charge transmission in devices is also investigated in simple model according to a junctionless transistor principal.

No abstract

An open-ended coaxial sensor for the determination of complex permittivity and moisture content of oil palm fruits is presented in this paper. The measurement system consisting of the sensor and a PC-controlled vector network analyzer have been tested successfully on a range of oil palm fruits of various degrees of ripeness. The initial values of the complex permittivity were estimated using the admittance model of the sensor. The amount of moisture content was found by matching the values of permittivity from the quasistatic model with the permittivity of a dielectric mixture model using the moisture content values obtained from the standard oven drying method.

No abstract

No abstract

SummaryA double-lateral-gate p-type junctionless transistor is fabricated on a low-doped (1015) silicon-on-insulator wafer by a lithography technique based on scanning probe microscopy and two steps of wet chemical etching. The experimental transfer characteristics are obtained and compared with the numerical characteristics of the device. The simulation results are used to investigate the pinch-off mechanism, from the flat band to the off state. The study is based on the variation of the carrier density and the electric-field components. The device is a pinch-off transistor, which is normally in the on state and is driven into the off state by the application of a positive gate voltage. We demonstrate that the depletion starts from the bottom corner of the channel facing the gates and expands toward the center and top of the channel. Redistribution of the carriers due to the electric field emanating from the gates creates an electric field perpendicular to the current, toward the bottom of the channel, which provides the electrostatic squeezing of the current.

No abstract