Electrical property comparison and charge transmission in p-type double gate and single gate junctionless accumulation transistor fabricated by AFM nanolithography

Abstract

The junctionless nanowire transistor is a promising alternative for a new generation of nanotransistors. In this letter the atomic force microscopy nanolithography with two wet etching processes was implemented to fabricate simple structures as double gate and single gate junctionless silicon nanowire transistor on low doped p-type silicon-on-insulator wafer. The etching process was developed and optimized in the present work compared to our previous works. The output, transfer characteristics and drain conductance of both structures were compared. The trend for both devices found to be the same but differences in subthreshold swing, ‘on/off’ ratio, and threshold voltage were observed. The devices are ‘on’ state when performing as the pinch off devices. The positive gate voltage shows pinch off effect, while the negative gate voltage was unable to make a significant effect on drain current. The charge transmission in devices is also investigated in simple model according to a junctionless transistor principal.

Numerical investigation and comparison with experimental characterisation of side gate p-type junctionless silicon transistor in pinch-off state

“…4, offers the on/off ratio of 10 5 , which is not a very fast switching, and subthreshold slope (SS) of 130 mV/Dec. Although the SS value is higher than the best value in single crystal silicon devices [14] and recent JLTs [15,16], it is still comparable with the lowest reported value of vertical silicon nanowire array devices, and also is lower than the SS value reported in our previous work with larger gate gap [9].…”

“…The fabrication method was mentioned in our previous work [9] using LAO. In this work, the conductive AFM tip Au-coated was used to draw predesigned oxide pattern as the mask on SOI surface, which provided lower applied voltage (8 V) on the tip to achieve the proper thickness (3 nm), and higher oxide speed (0.6 mm/s) compared with our previous works with Cr/Pt-coated conductive AFM tip [7,9]. The oxide thickness entirely depends on the humidity, AFM tip voltage and exposing time.…”

“…In the etching process, in order to remove the undesired Si area, potassium hydroxide (KOH) was used as an etchant. The 30 wt% KOH solution implemented saturated with isopropyl alcohol (IPA) as initiator at 638C [9].…”

“…The operation of the device is elaborately explained in [9]. In on state, the neutral (undepleted) wire is instantaneously shaped between the source and the drain in region II for non-zero V DS .…”

“…We already reported fabrication of the p-type lateral gate(s) JLT device with simple structure, low doping concentration and no gate oxide layer [5][6][7][8]. The charge transmission of the device with overall comparison between the single gate and double gate structure was investigated in our latest work [9]. Although low concentration provides low current in 'on' state, however, since the device is designed to work as the pinch-off transistor [10], it can also provide low 'off' current and better channel depletion in the pinch-off condition.…”