Two planarization approaches of the oxide-filled trench isolation have been evaluated. Results show that the oxidefilled shallow-trench isolation technology based on a chemical-mechanical polishing (CMP) process is difficult to control and has a poor uniformity. It also results in a dishing effect in wide field regions. On the other hand, a new planarization process can achieve an excellent uniformity and fully planar surface by using a combination of a masking polysilicon layer based on a CMP process, selective wet etching for oxide refill on active regions, short-time CMP process for oxide refill, and reactive ion etching etchback. Results also show that the high breakdown yield of the gate oxide and the low leakage current of the nt/p junction diodes with the novel planarization process demonstrates extremely low defect density from this process. This new process is a very promising candidate for oxide-filled shallow-trench isolation.
Shallow-trench isolation processes which involve refilling using deposition of oxide and polysilicon were investigated. Our results show that the oxide-filled shallow-trench isolation technology based on chemical-mechanical polishing (CMP) is difficult to control and results in poor uniformity. Use of this technology also involves in the dishing effect in wide field regions. However, shallow-trench isolation technology using a masking nitride layer, polysilicon refill, the CMP process with high etch selectivity, and local oxidation of polysilicon is easily implemented and absolutely field oxide encroachment (bird's beak) free. Although the CMP process results in the dishing effect in wide field regions, the local oxidation of polysilicon can reduce the amount of dishing. The polysilicon-filled shallow-trench isolation process can also achieve excellent uniformity across 6-inch diameter silicon wafers due to the high etching selectivity of polysilicon to chemical-vapor-deposited (CVD) oxide and SiN. Moreover, the n+/p junction leakage current of polysilicon-filled shallow trenches is comparable to that of oxide-filled shallow trenches. This simple and easily controllable process is a very promising candidate for shallow trench isolation.
The planarization of trench isolation refilled by deposition of polysilicon was investigated. Results show that the planarization by RIE etching has poor surface planarity. On the other hand, an excellent surface planarity can be achieved by the CMP process resulting from the high etching selectivity of polysilicon to nitride. This simple process provides a very promising candidate for trench isolation.) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 192.236.36.29 Downloaded on 2015-04-10 to IP
A high performance top-gate thin film transistor (TFT) has been fabricated using an as-deposited polycrystalline silicon (poly-Si) film by ultrahigh-vacuum chemical vapor deposition (UHV/CVD) followed by chemical mechanical polishing (CMP). In this process, due to the ultraclean environment and very low-pressure deposition of UHV/CVD, high-quality poly-Si films can be obtained and no long-term or post-recrystallization in channel films is needed. Maximum field effect mobilities of 58 cm2/V·s and 98 cm2/V·s for p- and n-channel TFTs, respectively, an ON/OFF current ratio of 1.1×107 for both p- and n-channels, and threshold voltages of -0.54 V for p-channel and 0.36 V for n-channel devices, respectively, are achieved. Finally, an analytical model of poly-Si TFTs was used to simulate the gate-voltage-dependent activation energy on the threshold and above the threshold regions and showed good agreement.
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