This paper presents a general and hybrid (centralized and distributed) approach for the activation of processing elements (PEs) inside of a processor array using the polytope model. The proposed approach is suitable of being implemented on reconfigurable systems since by changing some mathematical expressions, the proposed control approach is able to provide activation patterns for different algorithms based on the polytope model. We have taken the Cholesky decomposition as example for developing our hybrid control towards a generalization of this scheme.
Abstract:The problem of generating memory interfaces between loop-based accelerators and external memory is gaining the attention from the high-level synthesis research community. This paper presents an external memory system for inserting/extracting data to/from a loop-based accelerator derived by a high-level synthesis approach. The memory system is composed by four architectural cases which could occur during hardware synthesis. The memory system is based on a global asynchronous local synchronous approach and the use of dualport memory banks. FPGA-based implementation results show that the proposed memory system is technologically achievable and provides a high-bandwidth without introducing communication overhead.
Matrix algorithms are an important part of many digital signal processing applications as they are core kernels that usually need to be applied many times. Hardware assisted implementations using FPGAs provide a good compromise between performance, cost and power consumption. This paper presents a high level synthesis approach to generate embedded processor arrays for matrix algorithms based on the polytope model. The proposed approach provides a solution for efficient data memory accesses and data transferring for feeding the processor array, as well as it provides support for solving a set of problem size depending on FPGA available resources. The proposed approach has been validated by generating processor arrays for two case studies targeted for a Spartan-6 device. Results show that the implemented array outperforms hardware and software implementations targeted to embedded platforms as well.
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