Recently, the demand for miniaturized and fast transient response power delivery systems has been growing in high-voltage industrial electronics applications. Gallium Nitride (GaN) FETs showing a superior figure of merit (R ds,ON X Q g ) in comparison with silicon FETs [1] can enable both high-frequency and high-efficiency operation in these applications, thus making power converters smaller, faster and more efficient. However, the lack of GaNcompatible high-speed gate drivers is a major impediment to fully take advantage of GaN FET-based power converters. Conventional high-voltage gate drivers usually exhibit propagation delay, t delay , of up to several 10s of ns in the level shifter (LS), which becomes a critical problem as the switching frequency, f SW , reaches the 10MHz regime. Moreover, the switching slew rate (SR) of driving GaN FETs needs particular care in order to maintain efficient and reliable operation. Driving power GaN FETs with a fast SR results in large switching voltage spikes, risking breakdown of low-V gs GaN devices, while slow SR leads to long switching rise time, t R , which degrades efficiency and limits f SW . In [2], large t delay and long t R in the GaN FET driver limit its f SW to 1MHz. A design reported in [3] improves t R to 1.2ns, thereby enabling f SW up to 10MHz. However, the unregulated switching dead time, t DT , then becomes a major limitation to further reduction of t delay . This results in limited f SW and narrower range of V IN -V O conversion ratio. Interleaved multiphase topologies can be the most effective way to increase system f SW . However, each extra phase requires a capacitor for bootstrapped (BST) gate driving which incurs additional cost and complexity of the PCB design. Moreover, the requirements of f SW synchronization and balanced current sharing for high f SW operation in multiphase implementation are challenging.To mitigate the challenge associated with large t delay of the gate driver, which is dominated by the high-voltage LS, we propose a sub-ns delay BST GaN FET driver with dynamic LS in Fig. 16.7.1. During the turn-on period (DT) of the high-side switch (V SWH goes high), a large dynamic current, I d , is first mirrored to the output of LS. This I d is sustained until capacitor, C d , (placed at the source of LDMOS, M ld1 ) charges up, achieving a fast level-shifting at the output, V SWHb . When V SWHb reaches the BST supply level, and turns on the high-side GaN FET, only a small static current, I S , holds the turn-on state of the LS until V SWH goes low, minimizing the power dissipation. The upper current mirror is implemented with low-voltage devices, M 1 and M 2 , for faster response since the drain of M 2 is limited to V LX +V GS by DEPMOS, M dep1 . When V SWH goes low, M ld2 pulls down V SWHb , turning off the high-side GaN FET. Furthermore, an active BST switch is realized with use of a secondary sub-ns delay dynamic LS. Replacing the BST diode with a switch eliminates a diode drop on the BST supply rail, achieving low conduction loss of the hig...
