Quoting the International Technology Roadmap for Semiconductors (ITRS) 2009 Emerging Research Devices section, 'Nanomagnetic logic (NML) has potential advantages relative to CMOS of being non-volatile, dense, low-power, and radiation-hard. Such magnetic elements are compatible with MRAM technology, which can provide input–output interfaces. Compatibility with MRAM also promises a natural integration of memory and logic. Nanomagnetic logic also appears to be scalable to the ultimate limit of using individual atomic spins.' This article reviews progress toward complete and reliable NML systems. More specifically, we (i) review experimental progress toward fundamental characteristics a device must possess if it is to be used in a digital system, (ii) consider how the NML design space may impact the system-level energy (especially when considering the clock needed to drive a computation), (iii) explain--using both the NML design space and a discussion of clocking as context—how reliable circuit operation may be achieved, (iv) highlight experimental efforts regarding CMOS friendly clock structures for NML systems, (v) explain how electrical I/O could be achieved, and (vi) conclude with a brief discussion of suitable architectures for this technology. Throughout the article, we attempt to identify important areas for future work.

Layered 2-D crystals embrace unique features of atomically thin bodies, dangling bond free\ud interfaces, and step-like 2-D density of states. To exploit these features for the design of a steep slope\ud transistor, we propose a Two-dimensional heterojunction interlayer tunneling field effect transistor (Thin-\ud TFET), where a steep subthreshold swing (SS) of ∼14 mV/dec and a high on-current of ∼300 μA/μm are\ud estimated theoretically. The SS is ultimately limited by the density of states broadening at the band edges\ud and the on-current density is estimated based on the interlayer charge transfer time measured in recent\ud experimental studies. To minimize supply voltage VDD while simultaneously maximizing on currents,\ud Thin-TFETs are best realized in heterostructures with near broken gap energy band alignment. Using\ud the WSe2/SnSe2 stacked-monolayer heterostructure, a model material system with desired properties for Thin-TFETs, the performance of both n-type and p-type Thin-TFETs is theoretically evaluated. Nonideal effects such as a nonuniform van der Waals gap thickness between the two 2-D semiconductors and finite total access resistance are also studied. Finally, we present a benchmark study for digital applications, showing the Thin-TFETs may outperform CMOS and III–V TFETs in term of both switching speed and energy consumption at low-supply voltages

No abstract

No abstract

No abstract