Analog Circuit Design Using Tunnel-FETs

Sedighi, Behnam; Hu, Xiaobo Sharon; Liu, Huichu; Nahas, Joseph; Niemier, Michael

doi:10.1109/tcsi.2014.2342371

Cited by 106 publications

(63 citation statements)

References 25 publications

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“…As pointed out in [13][14][15], established design methodologies and tools as well as compact equations representing the device response in all the biasing design space are often required by analog IC designers as a guide for performing optimal circuit design. Here we discuss the gm/Id method and a compact device-model as some of such tools enabling TFET-based analog circuit design.…”

Section: The / Integrated Circuit Design Methods Applied To Tfetsmentioning

confidence: 99%

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TFET-Based Circuit Design Using the Transconductance Generation Efficiency <inline-formula> <tex-math notation="LaTeX">$ {g}_{m}/ {I}_{d}$ </tex-math></inline-formula> Method

Barboni

Siniscalchi

Sensale‐Rodriguez

2015

IEEE J. Electron Devices Soc.

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Tunnel field effect transistors (TFETs) have emerged as one of the most promising post-CMOS transistor technologies. In this work we: (i) review the perspectives of such devices for low-power high-frequency analog IC applications (e.g. GHz operation with sub-0.1 mW power consumption), (ii) discuss and employ a compact TFET device model in the context of the gm/Id integrated analog circuit design methodology, and (iii) compare several proposed TFET technologies for such applications. The advantages of TFETs arise since these devices can operate in the sub-threshold region with larger transconductance-to-current ratio than traditional FETs, which is due to the current turn-on mechanism being inter-band tunneling rather than thermionic emission. Starting from TCAD and/or analytical models for Si-FinFETs, graphene nano-ribbon (GNR) TFETs, and InAs/GaSb TFETs at the 15-nm gate-length node, as well as InAs double-gate (DG) TFETs at the 20-nm gatelength node, we conclude that GNR TFETs might promise larger bandwidths at low voltage drives due to their high current densities in the sub-threshold region. Based on this analysis and on theoretically predicted properties, GNR TFETs are identified as one of the most attractive field effect transistor technologies proposed-to-date for ultra-low power analog applications.Index Terms-Si-FinFETs, Tunnel-FET, ultra low power design, gm/Id method, one-stage common-source amplifier, twostage OTA with Miller effect compensation.

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Section: The / Integrated Circuit Design Methods Applied To Tfetsmentioning

confidence: 99%

“…In terms of more complex circuits, a TFET differential folded cascode OTA is presented in [14] to show the benefits of TFETs having a higher gm/Id than traditional FETs. At a given bias current, the DC gain, bandwidth, noise performance and offset improve by increasing the transconductance of the input transistors.…”

Section: Shown Inmentioning

confidence: 99%

TFET-Based Circuit Design Using the Transconductance Generation Efficiency <inline-formula> <tex-math notation="LaTeX">$ {g}_{m}/ {I}_{d}$ </tex-math></inline-formula> Method

Barboni

Siniscalchi

Sensale‐Rodriguez

2015

IEEE J. Electron Devices Soc.

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“…In those low-power applications, ADCs are the most critical and power-hungry blocks. Furthermore, the use of TFETs can enhance the analog circuit performance [22].…”

Section: Mixed-signal Circuitsmentioning

confidence: 99%

Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things

et al. 2017

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Abstract:In this review article for Internet of Things (IoT) applications, important low-power design techniques for digital and mixed-signal analog-digital converter (ADC) circuits are presented. Emerging low voltage logic devices and non-volatile memories (NVMs) beyond CMOS are illustrated. In addition, energy-constrained hardware security issues are reviewed. Specifically, light-weight encryption-based correlational power analysis, successive approximation register (SAR) ADC security using tunnel field effect transistors (FETs), logic obfuscation using silicon nanowire FETs, and all-spin logic devices are highlighted. Furthermore, a novel ultra-low power design using bio-inspired neuromorphic computing and spiking neural network security are discussed.

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“…TFET shows strong promises for ultra-low power applications. Previous research has demonstrated the use of TFETs to efficiently design logic circuit [18] and analog circuits such as DRAM, amplifier, ADC, [19,20]. Furthermore, TFETs conduct current through band-to-band tunneling which has very weak sensitivity to temperature variation [17].…”

Section: Background 21 Conventional Cnnmentioning

confidence: 99%

TFET-based Operational Transconductance Amplifier Design for CNN Systems

Lou

Palit

Horváth

et al. 2015

Proceedings of the 25th Edition on Great Lakes Symposium on VLSI

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A Cellular Neural Network (CNN) is a powerful processor that can significantly improve the performance of spatiotemporal applications such as pattern recognition, image processing, motion detection, when compared to the more traditional von Neumann architecture. In this paper, we show how tunneling field effect transistors (TFETs) can be utilized to enhance the performance of CNNs. Specifically, power consumption of TFET-based CNNs can be significantly lower when compared to MOSFET-based CNNs due to improved voltage controlled current sources (VCCSs) -an important component in CNN systems. We demonstrate that CNNs can benefit from low power conventional linear VCCSs implemented via TFETs. We also show that TFETs can be useful to realize non-linear VCCSs, which are either not possible or exhibit degraded performance when implemented via CMOS. Such non-linear VCCSs help to improve the performance of certain CNN operations (e.g., global maximum/minimum). We provide two case studiesimage contrast enhancement and maximum row selectionthat illustrate the benefits of non-linear VCCSs (e.g., reduced computation time, energy dissipation, etc.) when compared to CMOS-based approaches.

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Analog Circuit Design Using Tunnel-FETs

Cited by 106 publications

References 25 publications

TFET-Based Circuit Design Using the Transconductance Generation Efficiency <inline-formula> <tex-math notation="LaTeX">$ {g}_{m}/ {I}_{d}$ </tex-math></inline-formula> Method

TFET-Based Circuit Design Using the Transconductance Generation Efficiency <inline-formula> <tex-math notation="LaTeX">$ {g}_{m}/ {I}_{d}$ </tex-math></inline-formula> Method

Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things

TFET-based Operational Transconductance Amplifier Design for CNN Systems

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