In this work, we compare the electrical characteristics of MoS2 field-effect transistors (FETs) with Ag source/drain contacts with those with Ti and demonstrate that the metal-MoS2 interface is crucial to the device performance. MoS2 FETs with Ag contacts show more than 60 times higher ON-state current than those with Ti contacts. In order to better understand the mechanism of the better performance with Ag contacts, 5 nm Au/5 nm Ag (contact layer) or 5 nm Au/5 nm Ti film was deposited onto MoS2 monolayers and few layers, and the topography of metal films was characterized using scanning electron microscopy and atomic force microscopy. The surface morphology shows that, while there exist pinholes in Au/Ti film on MoS2, Au/Ag forms a smoother and denser film. Raman spectroscopy was carried out to investigate the metal-MoS2 interface. The Raman spectra from MoS2 covered with Au/Ag or Au/Ti film reveal that Ag or Ti is in direct contact with MoS2. Our findings show that the smoother and denser Au/Ag contacts lead to higher carrier transport efficiency.

The scanning microwave microscope is used for calibrated capacitance spectroscopy and spatially resolved dopant profiling measurements. It consists of an atomic force microscope combined with a vector network analyzer operating between 1–20 GHz. On silicon semiconductor calibration samples with doping concentrations ranging from 1015 to 1020 atoms/cm3, calibrated capacitance-voltage curves as well as derivative dC/dV curves were acquired. The change of the capacitance and the dC/dV signal is directly related to the dopant concentration allowing for quantitative dopant profiling. The method was tested on various samples with known dopant concentration and the resolution of dopant profiling determined to 20% while the absolute accuracy is within an order of magnitude. Using a modeling approach the dopant profiling calibration curves were analyzed with respect to varying tip diameter and oxide thickness allowing for improvements of the calibration accuracy. Bipolar samples were investigated and nano-scale defect structures and p-n junction interfaces imaged showing potential applications for the study of semiconductor device performance and failure analysis.

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We report the fabrication and characterization of Si nanowire memory devices with oxide/nitride/oxide stacked layers as the gate dielectrics and charge storage media. The devices were fabricated by using photolithography to pattern the metal contacts to the Si nanowires grown on pre-defined locations. A large memory window with high on/off-state current ratio due to the small radius and intrinsic doping of the Si nanowire is obtained. In addition, the simple reversible write/read/erase operations have been implemented with these memory devices. The dynamics of the nanowire/nitride charge exchange and its effect on the threshold voltage and memory retention have been investigated.