Reliable microfabrication processes and materials compatible with complementary metal-oxide semiconductor (CMOS) technology are required by industry for the mass production of complex and highly miniaturized lab-on-a-chip systems. Photopolymers are commonly used in the semiconductor industry, and are suitable for the integration of multilayer structures onto CMOS substrates. This paper describes a novel photopolymer bonding process compatible with CMOS technology for the fabrication of three-dimensional monolithic microfluidic devices. The process consists of the formation of a conformal adsorbate film (CAF) approximately 15 nm thick on a patterned photopolymer layer (KMPR), thereby increasing the number of open polymer chains at the bonding interface and acting as an ultra-thin adhesive layer. This thin adhesive layer is made of the same photopolymer as the microfluidic structures, but has a substantially lower crosslinking density so it will be able to make better bonds during a thermocompressive bonding step. This CAF treatment substantially improves the bonding yield between two patterned and previously crosslinked photopolymer layers because both optimum structure strength (to resist deformation during bonding) and bonding strength from epoxy crosslinking can be achieved. We demonstrate high bonding yields of up to 99% of the useful area of the substrate after three successive bonding steps. With this technique, up to six layers have been bonded in a single device. Unlike previously reported methods the quality of bonding is mostly decoupled from soft-bake parameters and crosslinking level of the previously patterned layers. Three different bonding processes were characterized to describe the bonding mechanism and the differences between the presented method and the partial-crosslinking bonding method. Capillary filling experiments were performed in microchannels of multilayer structures built with the CAF technique, without any observable leakage between layers.
The need for precise temperature control at small scales has provided a formidable challenge to the lab-on-chip community. It requires, at once, good thermal conductivity for high speed operation, good thermal isolation for low power consumption and the ability to have small (mm-scale) thermally independent regions on the same substrate. Most importantly, and, in addition to these conflicting requirements, there is a need to accurately measure the temperature of the active region without the need for device-to-device calibrations. We have developed and tested a design that enables thermal control of lab-on-chip devices atop silicon substrates in a way that could be integrated with the standard methods of mass-manufacture used in the electronics industry (i.e. CMOS). This is a significant step towards a single-chip lab-on-chip solution, one in which the microfluidics, high voltage electronics, optoelectronics, instrumentation electronics, and the world-chip interface are all integrated on a single substrate with multiple, independent, thermally-controlled regions based on active heating and passive cooling.
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