This paper describes an efticient Ethemet Medium Access Control (MAC) design, according to IEEE 802.3 standards for Fast Ethernet (100 M p s ) an IOBase-T (IO Mbps) implementations in full and half duplex modes, suitable for re-use as Intellechral Property (IP) core in
Svstem-on-Chip (SOC) designs. The description and contributed results exhibit that the main advantages of this design reside in a really low logic cost keeping a great tolerance far external clock changes, a suppression of high working clack ,frequencies and domains, and a high confgurability and flexibility for master processors interface.0-7803-8160-2/03/$17.00 02003 IEEE.
In this work we present a simulator for a multilevel cache memory system on a monoprocessor environment. It has incorporated a full graphic interface operating on a PC-DOS environment. At first, the simulator was conceived as a tool for applying it to teaching of cache memories. However, the potentiality of the developed system has proved its utility on program analysis and design strategies of memory systems. The above characteristics enable the simulator to be used for designing systems that run optimally a determinate kind of programs and improve the operating mode of a determinate architecture
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