Self-adaptive systems often use a middleware-based approach where adaptation mechanisms and policies are separated and externalized from the application code. Such separation facilitates the independent analysis of application and adaptation. In the QuA middleware, we use mirror-based reflection and service planning to support the development and execution of self-adaptive systems. A mirror provides meta information about a service's behavior and implementation throughout all life-cycle phases, including its performance in different contexts. Service planning supports dynamic discovery, utility-based and context-aware evaluation, and selection of alternative implementations of a given service.Here we argue that the QuA middleware is also able to support certain forms of evolution of adaptive systems. Since in QuA new implementation alternatives or updated versions of software are automatically discovered and considered during service planning, evolution both during run time and load time is supported. Experimental results from evolving a state-of-the-art adaptive media streaming application using our middleware are also presented.
Time-domain ADCs are increasing in popularity due in part to compatibility with deep sub-micron (DSM) CMOS technology. The performance of time-domain ADCs that use VCOs in open loop is to a large extent limited by the linearity of the output frequency of the VCO as a function of its control voltage. In this paper, we present an analysis of a system for VCO linearization, suppressing distortion and phase noise introduced by the VCO. We connect the noise from each component of the system to the performance of the ADC. Further, we demonstrate the feasibility of the system with transistor level simulations. We designed the simulated system for 12 bit linearity and simulated the transistor level model using a commercially available 90 nm CMOS process design kit (PDK).
In this paper we explore the noise and linearity limitations of a delay line based frequency to voltage converter (FVC) for use in an analog to digital converter (ADC) linearization system. Phase noise due to the delay line is the main source of noise in the FVC. In this paper we derive the relationship between the phase noise and the output voltage noise of the FVC. Furthermore, we characterize the constraints on the design of the delay line to ensure good linearity and derive a relationship between the series resistance of the buffer driving the output filter and the total harmonic distortion (THD). Simulation results obtained using a commercially available 90 nm process design kit (PDK) show good agreement between the predicted noise and linearity and the simulated results.
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