Moore's Law states that transistor density will double every two years, which is sustained until today due to continuous multidirectional innovations (such as extreme ultraviolet lithography, novel patterning techniques etc.), leading the semiconductor industry towards 3 nm node (N3) and beyond. For any patterning scheme, the most important metric to evaluate the quality of printed patterns is edge placement error, with overlay being its largest contribution. Overlay errors can lead to fatal failures of IC devices such as short circuits or broken connections in terms of pattern-to-pattern electrical contacts. Therefore, it is essential to develop effective overlay analysis and control techniques to ensure good functionality of fabricated semiconductor devices. In this work we have used an imec N-14 BEOL process flow using litho-etch-litho-etch (LELE) patterning technique to print metal layers with minimum pitch of 48nm with 193i lithography. Fork-fork structures are decomposed into two mask layers (M1A and M1B) and then the LELE flow is carried out to make the final patterns. Since a single M1 layer is decomposed into two masks, control of overlay between the two masks is critical. The goal of this work is of two-fold as, (1) to quantify the impact of overlay on capacitance and (2) to see if we can predict the final capacitance measurements with selected machine learning models at an early stage. To do so, scatterometry spectra are collected on these electrical test structures at (a) post litho, (b) post TiN hardmask etch, and (c) post Cu plating and CMP. Critical Dimension (CD) and overlay measurements for line/space (L/S) pattern are done with SEM post litho, post etch and post Cu CMP. Various machine learning models are applied to do the capacitance prediction with multiple metrology inputs at different steps of wafer processing. Finally, we demonstrate that by using appropriate machine learning models we are able to do better prediction of electrical results.
Background: The chemically amplified resist (CAR) has been the workhorse of lithography for the past few decades. During the evolution of projection lithography to extreme ultraviolet lithography (EUVL), a continuous reduction in feature size is observed. Also, a reduction in resist film thickness (FT) is required to prevent large aspect ratios that lead to pattern collapse. A further reduction in resist FT, into an ultrathin film regime (<30 nm resist FT), is expected when advancing to high NA EUVL. This brings along associated challenges with (1) resist critical dimension scanning electron microscope (CDSEM) metrology and (2) resist patterning performance.Aim: Assessment of metrology challenges and patterning limits of a CAR working in this ultrathin film regime. Deconvoluting the metrology and patterning effect on the determination of the unbiased line width roughness (uLWR).Approach: Patterning a CAR at different nominal resist FTs on two different underlayers to quantify the changes in CDSEM image quality and resist patterning performance with the resulting uLWR changes. Results:The CDSEM image signal-to-noise ratio (SNR) depends on resist FT and the underlayer. The uLWR increases with a reduction in resist FT but scales differently on the two underlayers.Conclusions: A relationship between CDSEM image SNR and uLWR is found. The SNR and uLWR scaling difference on the two underlayers, as well as the uLWR dependency on SNR was determined to be a metrology effect. The general uLWR increase for a reduced resist FT was determined to be a patterning effect.
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