We present measurements of the thermal conductance of self-assembled monolayer (SAM) junctions formed between metal leads (Au, Ag, Pt, and Pd) with mismatched phonon spectra. The thermal conductance obtained from frequency domain thermoreflectance experiments is 65 ± 7 MW/m(2) K for matched Au-alkanedithiol-Au junctions, while the mismatched Au-alkanedithiol-Pd junctions yield a thermal conductance of 36 ± 3 MW/m(2) K. The experimental observation that junction thermal conductance (per molecule) decreases as the mismatch between the lead vibrational spectra increases, paired with results from molecular dynamics (MD) simulations, suggest that phonons scatter elastically at the metal-SAM interfaces. Furthermore, we resolve a known discrepancy between measurements and MD predictions of SAM thermal conductance by using a contact mechanics model to predict 54 ± 15% areal contact in the Au-alkanedithiol-Au experimental junction. This incomplete contact obscures the actual junction thermal conductance of 115 ± 22 MW/m(2) K, which is comparable to that of metal-dielectric interfaces.

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This work formulates a rough surface contact model that accounts for adhesion through a Morse potential and plasticity through the Kogut-Etsion finite element-based approximation. Compared to the commonly used Lennard-Jones (LJ) potential, the Morse potential provides a more accurate and generalized description for modeling covalent materials and surface interactions. An extension of this contact model to describe composite layered surfaces is presented and implemented to study a self-assembled monolayer (SAM) grown on a gold substrate placed in contact with a second gold substrate. Based on a comparison with prior experimental measurements of the thermal conductance of this SAM junction [Majumdar et al., Nano Lett. 15, 2985-2991 (2015)], the more general Morse potential-based contact model provides a better prediction of the percentage contact area than an equivalent LJ potential-based model. V

A new multiphysics, multiscale framework is presented which is capable of capturing and predicting both wafer-scale and feature-scale defects. Through physics-based modeling, the empirical wear/Preston coefficient often found in popular feature scale models has been eliminated. Simulation results show the topography evolution of an actual metal 1 layout between two dies located in different positions on a wafer during the CMP process.