Future development of the modern nanoelectronics and its flagships internet of things, artificial intelligence, and neuromorphic computing is largely associated with memristive elements, offering a spectrum of inevitable functionalities, atomic level scalability, and low-power operation. However, their development is limited by significant variability and still phenomenologically orientated materials’ design strategy. Here, we highlight the vital importance of materials’ purity, demonstrating that even parts-per-million foreign elements substantially change performance. Appropriate choice of chemistry and amount of doping element selectively enhances the desired functionality. Dopant/impurity-dependent structure and charge/potential distribution in the space-charge layers and cell capacitance determine the device kinetics and functions. The relation between chemical composition/purity and switching/neuromorphic performance is experimentally evidenced, providing directions for a rational design of future memristive devices.

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Computation-In-Memory (CIM) using memristive devices is a promising approach to overcome the performance limitations of conventional computing architectures introduced by the von Neumann bottleneck which are also known as memory wall and power wall. It has been shown that accelerators based on memristive devices can deliver higher energy efficiencies and data throughputs when compared with conventional architectures. In the vast multitude of memristive devices, bipolar resistive switches (BRS) based on the valence change mechanism (VCM) are particularly interesting due to their low power operation, non-volatility, high integration density and their CMOS compatibility. While a wide range of possible applications is considered, many of them such as artificial neural networks heavily rely on Vector-Matrix-Multiplications (VMMs) as a mathematical operation. These VMMs are made up of large numbers of Multiplication and Accumulation (MAC) operations. The MAC operation can be realised using memristive devices in an analog fashion using Ohm’s law and Kirchhoff’s law. However, VCM devices exhibit a range of non-idealities, affecting the VMM performance, which in turn impacts the overall accuracy of the application. Those non-idealities can be classified into time-independent (programming variability) and timedependent (read disturb and read noise). Additionally, peripheral circuits such as Analog to Digital Converters (ADCs) can introduce errors during the digitalization. In this work, we experimentally and theoretically investigate the impact of deviceand circuit-level effects on the VMM in a VCM crossbars. Our analysis shows that the variability of the Low Resistive State (LRS) plays a key role and that reading in the RESET direction should be favored to reading in the SET direction.

The proliferation of machine learning algorithms in everyday applications such as image recognition or language translation has increased the pressure to adapt underlying computing architectures towards these algorithms. Application specific integrated circuits (ASICs) such as the Tensor Processing Units by Google, Hanguang by Alibaba or Inferentia by Amazon Web Services were designed specifically for machine learning algorithms and have been able to outperform CPU based solutions by great margins during training and inference. As newer generations of chips allow handling of and computation on more and more data, the size of neural networks has dramatically increased, while the challenges they are trying to solve have become more complex. Neuromorphic computing tries to take inspiration from biological information processing systems, aiming to further improve the efficiency with which these networks can be trained or the inference can be performed. Enhancing neuromorphic computing architectures with memristive devices as non-volatile storage elements could potentially allow for even higher energy efficiencies. Their ability to mimic synaptic plasticity dynamics brings neuromorphic architectures closer to the biological role models. So far, memristive devices are mainly investigated for the emulation of the weights of neural networks during training and inference as their non-volatility would enable both processes in the same location without data transfer. In this paper, we explore realisations of different synapses build from memristive ReRAM devices, based on the Valence Change Mechanism. These synapses are the 1R synapse, the NR synapse and the 1T1R synapse. For the 1R synapse, we propose three dynamical regimes and explore their performance through different synapse criteria. For the NR synapse, we discuss how the same dynamical regimes can be addressed in a more reliable way. We also show experimental results measured on ZrOx devices to support our simulation based claims. For the 1T1R synapse, we explore the trade offs between the connection direction of the ReRAM device and the transistor. For all three synapse concepts we discuss the impact of device-to-device and cycle-to-cycle variability. Additionally, the impact of the stimulation mode on the observed behavior is discussed.