Nowadays nanostructures play a vital part in the rapidly expanding areas of photovoltaics. The ability of nanowires to transfer photo-generated carriers rapidly across a solar cell has lead our interest in growth of nanowires . Currently Vapor Liquid Solid (VLS) epitaxy is the most common method used to grow epitaxial vertical nanowires. A metal particle such as gold is used to form a liquid alloy eutectic with the material of a substrate or with material supplied in the vapor phase. In growing semiconductor wires using metal droplets, it has been shown that the wires grow in the (111) direction and have clean facets . Furthermore these wires generally present an undesirable larger pyramidal base at the bottom and there is also evidence of surface migration of the metal catalyst. Thus far, most of the effort in the development of vertical III-V semiconductor nanowires has been limited to homo-polar combinations (e.g. InAs on InP). The ability to fabricate III-V nanowires on silicon could however pave the way toward the monolithic integration of III-V nanostructured solar cells with Si. Here we demonstrate the growth of GaAs and InP nanowires on silicon (111) using gold as the metal seed particle. An ordered array of gold nano dots is integrated on the surface of a silicon substrate using self-assembled polystyrene nanospheres as the Au evaporation template. The size of the gold dots range from 40 nm to 150 nm and the pitch is about 500 nm. The growth of the wires is done by chemical beam epitaxy under a vapour phase environment. Scanning electron microscopy and photoluminescence are used to characterize these nanowires. Wire exhibit high crystallinity and there is an absence of the pyramidal base at the bottom of the nanowire using this technique. Furthermore the study also shows evidence of pregrowth motion of some of the gold particles causing coalescence of nanowires and leading to the development of nanopods and tilted (off-normal) nanowires. Finally in the light of their optical properties the relevance of these wires to photovoltaic applications is discussed.
Nano-gap metal oxide semiconductor (MOS) capacitors were studied to evaluate their limitations in applications of dielectric spectroscopy in living cells. The purpose was to optimize the design of a transducer to avoid interfacial polarization at the electrodes. Silicon IC technology was selected for designing processes in which we could limit electric double layer impedance by precisely controlling dielectric thickness of the capacitors in the range of 17 to 150 nm. The working capacitance was defined by lateral oxide etching of capacitor structures of various configuration to ensure high perimeter to area ratio. Highly doped n+ polysilicon and n+ implanted Si substrate were acting as capacitor's electrodes. Restrictions known from CMOS circuits regarding oxide leakage current, which depends on geometry and increases with the gate area were taken into account. To allow for testing cells (yeasts), which have larger dimensions than nano structures it was necessary to include cell manipulation using dielectrophoresis (DEP). Entrapment of cells at the electrode perimeter preceded electrical measurements. Our focus in analyses was on the frequency dependence of impedance parameters.
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