An ultra-low power robust CMOS temperature sensor is presented for RFID. The BJT-based sensor employs a calibrated hybrid ADC, which combines a coarse 5-bit SAR conversion with a fine 9-bit deltasigma conversion. For the purpose of being robust, an error correction method is proposed in this paper, which can calibrate the SAR errors caused by power supply and mismatch. A smart clock generator is also proposed to adapt the change of PTAT bias current, which provides the integrators more settling time in low temperature with low bias current and makes the delta-sigma ADC faster in high temperature to reduce the error caused by leakage. The sensor has been implemented in a 130 nm CMOS process. After a one-point temperature trimming, the sensor has a resolution of 0.015 from −40°C to 85°C, and only consumes 10 µA from 1.5 V supply.
This paper presents a high-efficient energy harvest chain for ultra-low power passive UHF RFID tags. In this design, a high-efficiency differential-drive CMOS rectifier is adopted, a novel voltage limiter is used to provide a stable limiting voltage against temperature and process variation, and a voltage reference using peaking current source together with a high performance regulator with dynamic tail current source are utilized to meet the low-power low-voltage requirement. Measurement results show that the total current dissipation of our proposed energy harvest chain is less than 2.2511A with a peak power conversion efficiency (PCE) of 51.34%@-10dBm. This high-efficient energy harvest chain is designed and implemented in TSMC 0.18 11 m CMOS process with an area of 290l1m x 140l1m.
An ultra-compact transceiver structure for BCC (Body Channel Communication) is proposed and analyzed in this paper. The architecture of this transcei ver is mostly simplified compared with the conventi onal FS K transcei ver thanks to the reuse of the PLL circuit (phase-locked l oop) as modulator and demodulator. This will be very suitable for the human body communicati on which prefers the compact circuit structure and l ow power consumption. The whole BCC transceiver is anal yzed and simulated, proving the correct operation and the good feasibility.
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