A new 64-cell NAND flash memory with asymmetric S/D (Source/Drain) structure for sub-40nm node technology and beyond has been successfully developed. To suppress short channel effect in NAND memory cell, asymmetric S/D consisting of optimized junction and inversion layer induced by fringe field of WL bias which is applied at NAND operation conditions is successfully utilized. 64-cell NAND string which is double number of cells used in current NAND string is also used to further reduce bit cost by achieving over 10% chip size reduction while almost maintaining MLC (Multi-Level-Cell) NAND performance requirements.
In order to develop high density NAND Flash device, the increased number of cell strings for 1 pag e buffer f orces to _ form a long bit-line with low sheet resistance, as well as low SitD parasitic capacitance between bit-lines. In this paper, we D secured a copper damascene process to form 38nm bit-lines(1) Photo Resist patterning with 76nm pitch using SADP (Self-Aligned Double Patterning) process. The methods to minimize the sheet resistance and to suppress the parasitic capacitance were explained on NAND Flash device with 38nm node technology.
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