Synchronous pulse operation upon both source and bias RFs for inductively coupled plasma (ICP) etching system, having both dynamic matching networks and RF frequency-sweeping to ensure the lowest RF reflected power, is introduced for the first time. A superior performance of synchronous pulse operation to conventional continuous wave (cw) as well as source pulse operations is confirmed through plasma diagnostics by using Langmuir probe, plasma simulation by using hybrid plasma equipment model (HPEM) and etching performance. Significant reduction of RF power reflection during pulse operation as well as improvement of 35 nm gate critical dimension (CD) uniformity for sub-50 nm dynamic random access memory (DRAM) are achieved by adapting synchronous pulse plasma etching technology. It is definitely expected that synchronous pulse plasma system would have a great ability from a perspective of robustness on fabrication site, excellent gate CD controllability and minimization of plasma induced damage (PID) related device performance degradation.
Highly manufacturable partially insulated field-effect transistors (PiFETs) were fabricated by using Si-SiGe epitaxial growth and selective SiGe etch process. Owing to these technologies, pseudo-silicon-on-insulator (SOI) structures, partially insulating oxide (PiOX) under source/drain (PUSD) and PiOX under channel (PUC), could be easily realized with excellent structural and process advantages. We are demonstrating their preliminary characteristics and properties. Especially, in the PUSD PiFET, junction capacitance, leakage current, and DIBL in bulk devices could be reduced and the floating body problem in SOI devices was also cleared without any area penalty. Thus, this PiFET structure can be a promising candidate for the future DRAM cell transistor.
Index Terms-Epitaxial growth, partially insulated field-effect transistors (PiFETs), partially insulating oxide (PiOX), PiOX under channel (PUC), PiOX under source/drain (PUSD), SiGe.
This paper presents the trap layer engineered body-tied FinFET device for MLC NAND Flash application. The device design parameters for high density NAND Flash memory have been considered, and the advantages of FinFET structure and high-k blocking dielectric in such device have been demonstrated. Based on the WN nano-dot memory device, the trap layer engineering using nitride layer has been performed, and the results show that the memory window is improved from 2.6 V to 7.8 V by utilizing engineered trap layer at 14 MV/cm F-N programming, and it is proposed as a possible MLC NAND device structure.
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