Trap Layer Engineered FinFET NAND Flash with Enhanced Memory Window

Abstract

This paper presents the trap layer engineered body-tied FinFET device for MLC NAND Flash application. The device design parameters for high density NAND Flash memory have been considered, and the advantages of FinFET structure and high-k blocking dielectric in such device have been demonstrated. Based on the WN nano-dot memory device, the trap layer engineering using nitride layer has been performed, and the results show that the memory window is improved from 2.6 V to 7.8 V by utilizing engineered trap layer at 14 MV/cm F-N programming, and it is proposed as a possible MLC NAND device structure.

Comparative Study of Charge Trapping Type SOI-FinFET Flash Memories with Different Blocking Layer Materials

“…Moreover, threshold voltage (V t ) variability in the FinFETs and TG devices is much smaller than that in the conventional bulk planar MOSFETs because the random dopant fluctuation (RDF) induced V t variation is negligible in the FinFETs and TG devices due to the undoped fin-channels [14][15][16][17][18][19][20][21][22]. Therefore, the scaled charge trapping (CT) type fin-channel flash memories using silicon on insulator (SOI)-based fin-channels and body-tied bulk Si fin-channels have actively been developed [23][24][25][26][27][28][29][30][31][32]. However, a high-k blocking layer is strongly required in the ultimately scaled CT type flash memory fabrication to overcome the gate coupling area decrease with scaling down the device size [33].…”

Experimental study of three-dimensional fin-channel charge trapping flash memories with titanium nitride and polycrystalline silicon gates

“…[13][14][15][16][17][18][19] Therefore, scaled fin-channel flash memory cell transistors using siliconon-insulator (SOI)-based and body-tied bulk silicon (Si) fin channels have been actively developed, and the scalability of fin-channel flash memories down to a gate length (L g ) of 20 nm has been demonstrated. [20][21][22][23][24][25][26][27][28][29] However, the gate material dependence of the electrical characteristics of SOIbased FinFET flash memories has not been investigated sufficiently. Very recently, we have developed floating-gate (FG)-type crystalline-Si and polycrystalline-Si (poly-Si) finchannel flash memories with TG and DG structures, and confirmed that the TG structure has a larger memory window and a higher SCE immunity than the DG structure owing to the additional top gate and recessed buried oxide (BOX) region, which strengthen the controllability of the channel potential and increase the coupling ratio of the FG to the control gate (CG).…”

Impacts of Nanocrystal Location on the Operation of Trap-Layer-Engineered Poly-Si Nanowired Gate-All-Around SONOS Memory Devices

“…Recently, poly-Si-based SONOS device has attracted much attention because of its full process compatibility with 3-D integration [5], [6]. Various approaches have been proposed for improving SONOS device performance such as enhancing gate controllability using multigated schemes such as gate-allaround (GAA) [7], replacing a block oxide layer with a high-k dielectric [8], or adopting a trap-layer-engineering (TLE) scheme [9]- [11]. The concept of TLE was originally proposed by incorporating the tungsten nitride nanodots in the nitride layer.…”

“…7(c)] devices show faster rates over the STD control. For the STD device, it has been pointed out previously that, during programming, the centroid of the trapped electrons in the nitride layer tends to migrate from the bottom interface toward the middle of the nitride layer [9]. Nevertheless, Si-NC dots in the bot-SN and mid-SN devices provide additional trapping sites in the bottom nitride interface and the nitride center, respectively; therefore, more electrons can be trapped in positions closer to the channel than the STD control during programming.…”