Major efforts are currently underway throughout the IC industry to develop the capability to integrate device chips by stacking them vertically and using through-silicon vias (TSVs). The resulting interconnect density, bandwidth, and compactness achievable by TSV technology exceed what is currently possible by other packaging approaches. Market-driven applications of TSV involving memory include multi-chip high-performance DRAM, integration of memory and logic functions for enhanced video on handheld devices, and stacked NAND flash for solidstate drives. High-volume commercial implementation of 3D TSV is imminent but faced by special challenges of design, fabrication, bonding, test, reliability, know-good die, standards, logistics, and overall cost. The main focus of this paper is the unit-process and process-integration technology required for TSV fabrication at the wafer level: deep silicon etching, dielectric via isolation, metallization, metal fill, and chemicalmechanical polishing.
Silicon On Insulator SOI technology allows for high performance by eliminating latch up in bulk CMOS, improving the short-channel e ect, and soft error immunity. However, the oating body e ect in SOI devices and the resulting hysteresis poses major challenges for dynamic circuit designers. In this paper, we describe implementation of a 64 bit adder and some of the techniques used to overcome the parasitic bipolar discharge e ect while maintaining performance.
For advanced binary and PSM mask etch, final profile control is critically important for achieving desired mask specifications. As an aid to attain profile control, an etch profile simulation method has been developed. The method starts with an initial photoresist profile and incorporates etch rate and directionality information to predict the final etch profile. In this paper, simulated results are compared to measured etch profiles for PSM substrates. The results highlight the importance and implications of incoming resist profile and etch selectivity on final profile.
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