Falls are a leading cause of unintentional injuries and can result in devastating disabilities and fatalities when left undetected and not treated in time. Current detection methods have one or more of the following problems: frequent battery replacements, wearer discomfort, high costs, complicated setup, furniture occlusion, and intensive computation. In fact, all non-wearable methods fail to detect falls beyond ten meters. Here, we design a house-wide fall detection system capable of detecting stumbling, slipping, fainting, and various other types of falls at 60 m and beyond, including through transparent glasses, screens, and rain. By analyzing the fall pattern using machine learning and crafted rules via a local, low-cost single-board computer, true falls can be differentiated from daily activities and monitored through conventionally available surveillance systems. Either a multi-camera setup in one room or single cameras installed at high altitudes can avoid occlusion. This system’s flexibility enables a wide-coverage set-up, ensuring safety in senior homes, rehab centers, and nursing facilities. It can also be configured into high-precision and high-recall application to capture every single fall in high-risk zones.

With a gap-fill friendly "V'" profile, HARP can address the stringent gap fill requirements from 20nm STI and 32nm/28nm PMD with gate first HKMG with not much limitation to spacing CD. The weakest line in the STI trench can be addressed by adding steam into deposition steps or post-dep steam annealing. Dep-etch-dep approach would help to extend the gap fill application of HARP process. But in FinFET STI or PMD with RMG integration where "V" shape profile is difficult to be realized due to their unique integration flows, a FCVD process is needed to fulfill the gap-fill requirement. Excellent FCVD gap-fill has been demonstrated in high AR ratio FinFET STI and PMD even with straight vertical or reentrant profile. Some integration challenges like poor wet resistance and FCVD induced structured bending are addressed.

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Self-aligned multiple patterning (SAMP) can enable the semiconductor scaling before EUV lithography becomes mature for industry use. Theoretically any small size of pitch can be achieved by repeating SADP on same wafer but with challenges of pitch walking and line cut since line cut has to be done by lithography instead of self-aligned method. Line cut can become an issue at sub-30nm pitch due to edge placement error (EPE). In this paper we will discuss some recent novel ideas on line cut after self-aligned multiple patterning.