There is a significant gap between the internal and external efficiencies of conventional GaN light-emitting diodes (LEDs). The reason for this shortfall is the narrow escape cone for light in high refractive index semiconductors. In this letter, the p-side- up GaN/sapphire LEDs with surface textured indium tin oxide (ITO) widow layers were investigated using natural lithography with polystyrene spheres as the etching mask. Under optimum etching conditions, the surface roughness of the ITO film can reach 140 nm while the polystyrene sphere on the textured ITO surface is maintained at about 250 - 300 nm in diameter. The output power of the ITO/GaN LED with and without surface texturing is 10.9, and 8.5 mW at 20 mA, respectively. The LEDs fabricated using the surface-textured ITO produced an output power that exceeded that of the planar-surface LED by about 28% at 20 mA. (c) 2005 American Institute of Physics

Three combinations of additives based on polyethylene glycol (PEG), Cl − ions, bis(3-sulfopropyl)disulfide (SPS), and Alcian Blue (ABPV) were used to fabricate the Cu plated layer. The additive combination was found to play an important role in the microstructural evolution of the Cu plated layer. The PC (PEG + Cl − ) case produced the Cu plated layer with grains of a smaller size and random morphology, while the PCS (PEG + Cl − + SPS) and PCSA (PEG + Cl − + SPS + ABPV) cases produced the Cu plated layers with grains of a larger size and faceted morphology. Experimental results based on metallurgical examination and trace element analysis indicated that the interfacial reactions between Sn and Cu plated layers strongly depended upon the additive combination used in the Cu plating solution, and the dependence was reasonably correlated with the grain morphology of the Cu plated layer combined with the incorporation of organic impurities.Cu is commonly used for conductors and metallizations in printed circuit board (PCB) and Si integrated-circuit (IC) chip due to its superior electrical conductivity and good wettability with solder materials. Sn is extensively used in microelectronic solders due to its suitable melting point, efficient mechanical property, and low cost. So, the Sn/Cu joints massively exist in the microelectronic products. To form a Sn/Cu joint, reflow is conducted during which the Sn melts and wets the Cu substrate. The intermetallic compounds (IMC) are usually formed as a result of the interfacial reaction between Sn and Cu. Related investigations have been extensively performed to provide helpful information for reliability evaluation of solder joints. [1][2][3][4][5][6][7] The Cu conductor and metallization on PCB and Si chip can be fabricated using various methods, among which electroplating is widely used due to economic consideration. Electroplating is an electrochemical process involving complicated interaction between various additives used in the Cu plating bath, such as suppressor, accelerator, and so on. These additives interacted with each other on the Cu surface and inevitably were partially incorporated into the Cu plated layer during electroplating. The incorporation of organic impurities in the Cu plated layers during plating was found to have significant effects on the interfacial reactions between Sn-based solder and Cu plated substrate. [8][9][10][11][12][13] The S residue of about 17 ppm was detected in the Cu plated layer when a high level (3 × 10 −5 M) of accelerator, SPS (bissodium sulfopropyldisulfide, C 6 H 12 O 6 S 4 Na 2 ), was added in the Cu plating bath. 8 Large amounts of void were formed at the Cu/Cu 3 Sn interface along with the solder/Cu interfacial reaction during 150 • C aging, which was attributed to the reduction of free energy barrier for void formation due to interfacial segregation of S. Voids were continuously formed during aging and merged into several gaps within the Cu-Sn IMCs, forming an alternating layered structure composed of gaps and IMCs at the Sn-3...

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