Because of the "Boltzmann tyranny" (i.e., the nonscalability of thermal voltage), a certain minimum gate voltage in metal-oxide-semiconductor (MOS) devices is required for a 10-fold increase in drain-to-source current. The subthreshold slope (SS) in MOS devices is, at best, 60 mV/decade at 300 K. Negative capacitance in organic/ferroelectric materials is proposed in order to address this physical limitation in MOS technology. Here, we experimentally demonstrate the steep switching behavior of a MOS device-that is, SS ∼ 18 mV/decade (much less than 60 mV/decade) at 300 K-by taking advantage of negative capacitance in a MOS gate stack. This negative capacitance, originating from the dynamics of the stored energy in a phase transition of a ferroelectric material, can achieve the step-up conversion of internal voltage (i.e., internal voltage amplification in a MOS device). With the aid of a series-connected negative capacitor as an assistive device, the surface potential in the MOS device becomes higher than the applied gate voltage, so that a SS of 18 mV/decade at 300 K is reliably observed.

No abstract

No abstract

Metal oxide semiconductors are important due to their diverse set of applications in (opto)­electronics including light-emitting diodes, solar cells, and thin film transistors (TFTs). However, compared to their n-type counterparts, p-type oxide thin films are less often reported, and there is a need for increased fundamental understanding of their process-structure–property relationships. In this study, p-type CuO x was grown by plasma-enhanced atomic layer deposition (PE-ALD) using different ratios of hydrogen and oxygen plasma and a nonfluorinated copper amidinate precursor. This approach, combined with postdeposition annealing, enables tuning of the phase, oxidation state, and morphology of the films. Here, we comprehensively investigate the coupled relationships between: (1) PE-ALD process parameters; (2) oxidation state, composition, and grain size; and (3) electronic properties of the films. Synchrotron X-ray absorption spectroscopy was performed to quantify the copper oxidation states. By varying the hydrogen:oxygen plasma ratio, the phase of CuO x can be controlled to form Cu, Cu2O, or CuO. Vacuum annealing resulted in an increase in grain size and reduction in copper oxidation state. To study the p-type semiconductor behavior, bottom-gate TFTs were fabricated, demonstrating characteristic I–V behavior with an on/off current ratio of ∼105 for the film with the largest Cu­(I) fraction and largest grain size.

No abstract

No abstract

No abstract

A negative capacitance field-effect transistor (FET) with sub-60 mV/decade subthreshold slope (SS) at different temperatures (i.e. 14.8 mV/decade at 300 K, 15.7 mV/decade at 360 K and 24.3 mV/decade at 400 K) is experimentally demonstrated. A detailed account of the fabrication process of a negative capacitor is first introduced, followed by the measurement setup for the negative capacitance FET. The impact of temperature on negative capacitance FETs is investigated: (i) the equation for the internal voltage gain in the FET as a function of temperature is derived using Gibbs free energy and (ii) internal voltage against gate voltage (V Int against V G ), internal voltage gain against gate voltage (dV Int /dV G against V G ) and drain current against gate voltage (I D against V G ) curves at different temperatures are measured. It is confirmed that internal voltage amplification can be achieved using the ferroelectric capacitor. However, the magnitude of the step-up voltage transformation is reduced, i.e. from 9.5 at 300 K to 2.6 at 400 K. Additionally, the SS is slightly increased (i.e. degrading from 14.8 mV/decade at 300 K to 24.3 mV/decade at 400 K) with increasing temperature; however, all SS values are better than the physical limits of SS as dictated by Boltzmann statistics.Introduction: State-of-the-art fin-shaped field-effect transistors (FETs) have the practical limitation of requiring a minimum power supply of ∼0.7-0.9 V in 22/20 and 16/14 nm complementary metal-oxide semiconductor (MOS) technology because of the Boltzmann transport limit (i.e. a subthreshold slope (SS) of at least 60 mV per decade at 300 K). To address this technical challenge, the concept of negative capacitance in MOS transistors was proposed [1]. Since then, this research area has received significant research attention and produced novel steep switching (i.e. SS <60 mV/decade at 300 K) devices to overcome the fundamental limits of MOS transistors. In this Letter, a negative capacitance FET with a sub-60 mV/decade SS at different temperatures is experimentally demonstrated. The impact of temperature on these negative capacitance FETs is also investigated.