It is the first time that the high-k/metal gate technology was used at peripheral transistors for fully integrated and functioning DRAM. For cost effective DRAM technology, capping nitride spacer was used on cell bit-line scheme, and single work function metal gate was employed without strain technology. The threshold voltage was controlled by using single TiN metal gate with La 2 O 3 and SiGe/Si epi technology. The optimized DRAM high-k/metal gate peripheral transistors showed current gains of 65%/55% and DIBL improvements of 52%/46% for nMOSFET and pMOSFET, respectively. The results in process yield, performance, and reliability characteristics of the technology on 4Gb DRAM have shown that the gate-first high-k/metal gate DRAM technology can be regarded as one of the major candidates for next-generation low power DRAM products.

Reduction of sidewall defect induced leakage currents by the use of nitrided field oxides in silicon selective epitaxial growth isolation for advanced ultralarge scale integration High density plasma deposited phosphosilicate glass as pre-metal dielectrics for advanced self-aligned contacts in sub 0.25 m device technology Etch rate control in a 27 MHz reactive ion etching system for ultralarge scale integrated circuit processing

The degradation of 0.13pm NMOS and PMOS transistors caused by microtrenching pT) under hot-carrier and Edge FN stress is studied. DAHC stress was found to he a sensitive technique for characterizing the NMOS transistors while Edge FN stress was more suitable for the PMOS transistors. Interface state generation was also identified as the dominant degradation mechanism.