We introduce error correcting 4/6 modulation codes for holographic data storage. Above all, the merit of the proposed modulation codes is that their trellis structure allows error correcting capability. The proposed codes also do not have any fatal (i.e., isolated pixels) two-dimensional intersymbol interference (2D ISI) patterns. The decoding scheme uses the Viterbi algorithm. As a result, the proposed codes have better performance than the conventional 6/8 and 4/6 modulation codes overall. #
Abstract-In high-speed printed circuit boards, the decoupling capacitors are commonly used to mitigate the power-bus noise that causes many signal integrity problems. It is very important to determine their proper locations and values so that the power distribution network should have low impedance over a wide range of frequencies, which demands a precise power-bus model considering the decoupling capacitors. However, conventional power-bus models suffer from various problems, i.e., the numerical analyzes require huge computation while the lumped circuit models show poor accuracy. In this paper, a novel power-bus model has been proposed, which simplifies the n-port Z-parameters of a power-bus plane to a lumped T-network circuit model. It exploits the pathbased equivalent circuit model to consider the interference of the current paths between the decoupling capacitors, while the conventional lumped models assume that all decoupling capacitors are connected in parallel, independently with each other. It also models the equivalent electrical parameters of the board parasitic precisely, while the conventional lumped models employ only the inter-plane capacitance of the power-ground planes. Although it is a lumped model for fast and easy calculation, experimental results show that the proposed model is almost as precise as the numerical analysis. Consequently, the proposed model enables a quick and accurate optimization of power distribution networks in the frequency domain by determining the locations and values of the decoupling capacitors.Index Terms-Decoupling capacitors, equivalent circuit model, power-bus distribution network.
In this paper, a small-area and low-power current readout circuit with a novel two-stage conversion method is presented for 64-channel CNT (carbon nanotube) sensor arrays. In the first stage, current of each CNT sensor is amplified by 64 active input current mirrors (AICMs). In the second stage, the amplified current is converted to a voltage level through the shared variable gain amplifier (S-VGA). Then the S-VGA output is digitalized by successive approximation register analog-to-digital converter (SAR-ADC). The proposed readout circuit significantly reduces chip area and power consumption, since VGA is shared over 64 channels and passive elements are used only in S-VGA. Fabricated chip area is 0.173 mm(2) in 0.13 μm CMOS technology. Measured power consumption and linearity error are 73.06 μW and 5.3%, respectively, at the input current range of 10 nA-10 μA and conversion rate of 640 samples/s. A prototype real-time CNT sensor system was implemented using the fabricated readout circuit, and successfully detected alcohol reaction.
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