The origin of 1∕f fluctuations in positive-negative-positive (PNP) polycrystalline silicon-emitter bipolar-junction transistors is described. The interfacial oxide (IFO) at the monosilicon–polycrystalline silicon interface is found to significantly affect the noise behavior. The low-frequency noise originates from two independent fluctuation mechanisms: in the diffusion and tunneling components of the base current noise power spectral density (SIB) and from the diffusion current and carrier number fluctuations in the collector current noise power spectral density (SIC). The Hooge noise parameters for electrons and holes are calculated from the diffusion fluctuation models for SIB and SIC, respectively. Noise measurements on devices with different sizes and different IFO thicknesses indicate that the fluctuations occur in the minority-carrier (electron) tunneling current component of SIB through the IFO. The thickness of the IFO is estimated using this noise model. The tunneling fluctuations dominate over the diffusion fluctuations for the smaller (0.7×0.7μm2) transistors, while the opposite is the case for the larger (0.7×100μm2) ones. The scaling effect on the noise performance of these transistors is discussed. The effect of the IFO on the dc characteristics and the noise behavior of the PNP transistors is compared to that of the negative-positive-negative (NPN) counterparts on the same wafer.
A peculiar temperature mismatch between a power LDMOS and its sense FET develops over time resulting in yield losses. The anomaly is traced to trapped charge in the power LDMOS that arises from a seemingly unrelated change in the hydrogen anneal temperature in the back end. The physical mechanism leading to the anomaly and the interaction between temperature mismatch and metal layout are presented.
I. INTRODUCTIONAs smart power IC's perform increasingly more demanding and sophisticated functions, current sensing is often a vital part of circuit design [1]. A current sensor can be used to monitor the load current and provide over-current protection and improved control. Most current sensors are either integrated in close proximity to or imbedded in the power devices. When the power device is MOS, the current ratio between the power FET and the sense FET is always lower than the ratio of the channel widths due to metal debiasing. When current sensing is required over a temperature range, the current ratio is further complicated by temperature variations in the MOS threshold, channel and drift-region mobilities, and metal and via resistances. Knowledge about the temperature-coefficient mismatch (TCMM) between power FET and sense FET becomes crucial for accurate temperature compensation. In this work, an anomalous TCMM is reported for a 50V LDMOS power FET, sense FET pair and the mechanism leading to the anomaly is explained.
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