Anomalous temperature behavior in LDMOS current sensing

Abstract

A peculiar temperature mismatch between a power LDMOS and its sense FET develops over time resulting in yield losses. The anomaly is traced to trapped charge in the power LDMOS that arises from a seemingly unrelated change in the hydrogen anneal temperature in the back end. The physical mechanism leading to the anomaly and the interaction between temperature mismatch and metal layout are presented. I. INTRODUCTIONAs smart power IC's perform increasingly more demanding and sophisticated functions, current sensing is often a vital part of circuit design [1]. A current sensor can be used to monitor the load current and provide over-current protection and improved control. Most current sensors are either integrated in close proximity to or imbedded in the power devices. When the power device is MOS, the current ratio between the power FET and the sense FET is always lower than the ratio of the channel widths due to metal debiasing. When current sensing is required over a temperature range, the current ratio is further complicated by temperature variations in the MOS threshold, channel and drift-region mobilities, and metal and via resistances. Knowledge about the temperature-coefficient mismatch (TCMM) between power FET and sense FET becomes crucial for accurate temperature compensation. In this work, an anomalous TCMM is reported for a 50V LDMOS power FET, sense FET pair and the mechanism leading to the anomaly is explained.

Sense Device Structure in Hybrid IGBT with Constant Current Sense Ratio for Entire Collector Current Range

“…In order to control the current for the switching device to be appropriate for various load, the ratio of main switching device current I CE to sense device current (Current Sensing Ratio; CSR) should be constant for the entire range of I CE [2,3]. Also, low temperature dependence of CSR is preferred [4].…”