Power metal oxide semiconductor field effect transistors with accurate current sensing function over a wide temperature range

Current sense dynamics during turn-on of power MOSFET

“…Attempts to decrease the temperature impact on CSR are conducted in power devices, including optimization of the sense cells [4], the location of the mirror within the die, or increasing the spacing between power and sense devices [5], including implantation layers around the sense cells. 2D [5] and 3D [6] studies are used to explain observed CSR anomalies with differences between the thermal behavior of the current flowing in the drift and access regions, and the parasitic conduction at the border of sense FET. The impact of layout, wafer thickness, on crosstalk interactions between adjacent on-chip power devices and respectively on CSR and its error ε ε ε εCSR is recently reported [7].…”