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Supplying cost effective testing for large application specific integrated circuits (ASICs) is one of the key challenges facing the semiconductor industry. Projections suggest that it will not be cost effective to continue in the current test direction. ASIC suppliers must be able to offer a flexible, cost-effective set of test solutions that will meet a variety of customer requirements. This paper presents some of the trade-offs used in developing optimal test strategies.

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Chair: Hamid Mahmoodi, San Francisco State UniversityCo-Chair: Jeanne Trinko Mechler, IBM With scaling of CMOS towards nano-scale technologies, device variability and reliability is emerging as a major challenge for circuit design in such technologies. Hence, accurate measurement and characterization of sources of device variations and reliability degradations is very critical for coming up with appropriate circuit design techniques to mitigate such device non-idealities, as well as to insure the device manufacturability and yield. This session presents cutting-edge papers on effective measurement methods for characterization of gate dielectric breakdown, threshold voltage variations, delay variations, and an effective testing of multi-core SOC under process variations.