High Speed Serdes Devices and Applications

Stauffer, D.; Mechler, J.T.; Sorna, M.; Dramstad, Kent; Ogilvie, C.R.; Amanullah, Mohammad; Rockrohr, James Donald

doi:10.1007/978-0-387-79834-9

Cited by 20 publications

(4 citation statements)

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“…Apart from the packaging technology, the system-level SiP integrator must choose a communication architecture and determine the appropriate physical layer communication technologies. Based on the whole SiP target functionality and performance, it could involve options like serializer/deserializer (SerDes) [37], peripheral component interconnect express (PCIe), advanced interface bus (AIB) [38], or universal chiplet interconnect express (UCIe) [39]. Amongst these interconnection technologies, network on chip (NoC) [40]- [42] is also gaining popularity as it allows for seamless integration and efficient communication between heterogeneous chips and IP blocks within the SiP.…”

Section: 5d Packagingmentioning

confidence: 99%

Advancing Trustworthiness in System-in-Package: A Novel Root-of-Trust Hardware Security Module for Heterogeneous Integration

Sami,

Zhang,

Shuvo

et al. 2024

IEEE Access

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The semiconductor industry has adopted heterogeneous integration (HI), incorporating modular intellectual property (IP) blocks (chiplets) into a unified system-in-package (SiP) to overcome the slowdown in Moore's Law and Dennard scaling and to respond to the increasing demand for advanced integrated circuits (ICs). Despite the manifold benefits of HI, such as enhanced performance, reduced area overhead, and improved yield, this transformation has also led to security vulnerabilities in the SiP supply chain and in-field operations, ranging from chiplet piracy and SiP reverse engineering (RE) to information leakage. Although conventional countermeasures provide the desired robustness for monolithic ICs, they are insufficient for addressing these challenges in the context of HI. To address these concerns, this paper presents a novel root-of-trust architecture, augmenting the process of integration using a centralized chiplet hardware security module (CHSM), aiming to provide comprehensive and robust protection throughout the SiP supply chain and in-field operations. Also, the proposed architecture equipped with the CHSM effectively addresses potential security breaches while providing robust protection against zero-day attacks through its reconfigurable capabilities. Throughout five detailed case studies, this paper performs a comprehensive security analysis to illustrate the resilience of CHSM against contemporary attack scenarios in the HI domain.

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Section: 5d Packagingmentioning

confidence: 99%

Advancing Trustworthiness in System-in-Package: A Novel Root-of-Trust Hardware Security Module for Heterogeneous Integration

Sami,

Zhang,

Shuvo

et al. 2024

IEEE Access

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“…SerDes links are a high data rate wire link widely spread among microelectronic chips. By passing data from parallel to serial (Serializing) at the transmission and from serial to parallel (Deserializing) at the receiver, they spare the amount of wires used, the area needed and electro-magnetic interference that occur when wires are set in parallel [1].…”

Section: Introductionmentioning

confidence: 99%

Bit error probability of a very high data rate, amplitude modulated, communication system affected by timing jitter

Miqueu,

Bclvèze,

Brossier

et al. 2023

2023 16th International Conference on Signal Processing and Communication System (ICSPCS)

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When designing communication links, rises the issue of the modulation type selection. As two kinds of disturbances, thermal noise and jitter, degrade Serializer/Deserializer (SerDes) link performance, this design step is not straight forward. Considering only M order Pulse Amplitude Modulation (M-PAM) in this work, we propose to give the analytical expression of the bit error probability (BEP) of a high speed SerDes link considering both disturbances. This way we will be able to foresee the performances of a SerDes link for a given modulation order and select the best one. The BEP computation differs from the literature as the high data rate prevents here the use of a matched filter at the reception. The analytical expression of the BEP is detailed. The Bit Error Rate (BER) is obtained via simulation. Reliability of the analytical expression is discussed by comparing theoretical and simulation results. We conclude that our analytical expression of the BEP stands for an upper performance limit that enables the ranking of various modulation orders.

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“…The serializer chip is used to convert the parallel data into the higher bit rate serial data stream, which is widely used in high-speed data transmission systems and becomes one of the key modules in the serial data communication ASICs. In terms of parallel-to-serial conversion realization, the core circuit mainly has three structures: the multi-phase structure [1,2], the shift register structure [2] and the tree structure [3]. The multi-phase structure requires multi-phase clocks to select different parallel input channels.…”

Section: Introductionmentioning

confidence: 99%

A 5-Gbps serializer ASIC in 130 nm for high-speed front-end readout applications

et al. 2022

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This paper presents the design and the test results of a low-power 5 Gbps 10:1 serializer chip with the self-check function based on a standard 130 nm CMOS technology. This serializer chip adopts a multi-level design scheme with a combination of the multi-phase structure (5:1 module) in the low data rate part and the tree structure (2:1 module) in the high date rate part. The high data rate 2:1 module adopts a latch-induced latency control circuit to ensure the timing margin across corners. The serializer chip has been fully tested, wide-open 5 Gbps output eye diagram has been captured, and the logic function has also been verified. The measured power consumption of the whole chip is 42 mW including Rx/Tx, and the power consumption of the serializer core is around 12.1 mW.

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High Speed Serdes Devices and Applications

Cited by 20 publications

References 0 publications

Advancing Trustworthiness in System-in-Package: A Novel Root-of-Trust Hardware Security Module for Heterogeneous Integration

Advancing Trustworthiness in System-in-Package: A Novel Root-of-Trust Hardware Security Module for Heterogeneous Integration

Bit error probability of a very high data rate, amplitude modulated, communication system affected by timing jitter

A 5-Gbps serializer ASIC in 130 nm for high-speed front-end readout applications

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