For manufacturers of consumer electronics, conformance testing of embedded software is a vital issue. To improve performance, parts of this software are implemented in hardware, often designed in the Hardware Description Language VHDL. Conformance testing is a time consuming and error-prone process. Thus automating (parts of) this process is essential.There are many tools for test generation and for VHDL simulation. However, most test generation tools operate on a high level of abstraction and applying the generated tests to a VHDL design is a complicated task. For each specific case one can build a layer of dedicated circuitry and/or software that performs this task. It appears that the A two-level approach to automated conformance testing ofVHDL designs 433 ad-hoc nature of this layer forms the bottleneck of the testing process. We propose a generic solution for bridging this gap: a generic layer of software dedicated to interface with VHDL implementations. It consists of a number of Von Neumannlike components that can be instantiated for each specific VHDL design. This paper reports on the construction of and some initial experiences with a concrete tool environment based on these principles.

In this paper we report on the applicability of a number of ISO-9646 techniques, concepts and automatic test-generation tools in the area of multimedia processing (MPEG2). Several concepts, such as PICS and PCO, and EFSM-based TICN generation carried over to this new domain very well. The PHACT tool environment, originally developed at Philips for hardware (VHDL) protocol testing, was adapted and used for test generation and test execution in the multimedia processing domain. The paper also highlights a number of interesting issues related to the usage of (E)FSMs, such as dealing with reactive behavior at a software API PCO and dealing with stream-PCOs. Multimedia streams were modeled as FSMs. This turned out to be a new application area for test generation from composite or product FSMs, a technique originating from the embedded testing method. The process followed for test preparation and test execution consists of seven phases, which are surveyed in the paper.

The C104 is an asynchronous 32-way dynamic packet routing chip. It has a 264 Mbytes/s bi-directional bandwidth and a 1 sec switching latency. It oers high-density costeective commodity communications, which allow large switching networks to be constructed. Results are presented on the performance of this switching technology within the context of future High Energy Physics level II and level III trigger data trac patterns.

The C104 is an asynchronous 32-way dynamic packet routing chip. It has a 264 Mbytes/s bi-directional bandwidth and a 1 sec switching latency. It oers high-density costeective commodity communications, which allow large switching networks to be constructed. Results are presented on the performance of this switching technology within the context of future High Energy Physics level II and level III trigger data trac patterns.(To b e submitted to Nuclear Instruments and Methods)