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This paper presents efficient of IF decimation filters architecture using Pipelinehterleaving (PI) technique in which the amount of multiplications is reduced by 50%. The decimation filters are important blocks in Software Radio terminals to process different communications standards like GSM, IS-95, and UMTS. These kinds of blocks are needed to process the I, and Q components on the digital down-converter. The proposed architecture is evaluated by MATLABB. This evaluation shows that the proposed structures can be utilized in a multimode fashion.The frequency response of the decimator filter for each standard is analyzed and the frequency response for the decimator filter using PI architectures is also evaluated. The new architecture offers saving of 50% the amount of multiplications compare to the traditional implementation.

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This paper proposes a reduction in complexity of decimation filter architectures used in multi-standard digital receiver, using IIR filters implemented as a sum of two all-pass filters. The decimation filters are an important block in devices, which want to establish communication using different standards. IIR filters are implemented on specific stages of multistage Pipeline/Interleaving structure, where high order of filters is power consuming and area demanding. Therefore, a major reduction in complexity is obtained. Regularity is an important property of all pass filters, which can be decomposed on first or second order all-pass transfer functions achieving more efficient implementation. The results presented are implemented in Pipeline/Interleaving architectures using specific decimation decomposition proposed previously [2], [3]. Reductions of 36%, 77%, and 80% are obtained compared with previous works, where basically these implementations are based on linear phase filters. The decimation filter architecture is simulated using Matlab.

This paper present an efficient polyphase multiplierless finite impulse response (FIR) architecture based on New Distributed Arithmetic (NEDA). The polyphase structure is based on the decomposition of the transfer function in subfilters connected in parallel. The multiplications involved on each subfilter are replaced by an adder array implemented by NEDA. These subblocks presents a different distribution of Is and Os on the NEDA matrix compared with the implementation of the filter in a direct form or transposed form. NEDA presents a bottleneck that is reduced by a balance between a larger filter order and a reduced coefficient wordlength size impacting the whole structure with this tradeoff. This new architecture involves a reduced number of adders in their implementation without significant overhead. The results presented are compared with previous approaches showing superior result around of 34% average reduction on the total number of adders. Additionally, the proposed design method for FIR filter is simple.