Efficient multistage decimation filter using pipeline/interleaving architectures for digital IF receiver

Tecpanecatl-Xihuitl, J. Luis; Bayoumi, Magdy

doi:10.1109/scs.2003.1226939

Cited by 2 publications

(7 citation statements)

References 2 publications

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“…1 (e) shows the system architecture which adopts the proposed two-stage digital I/Q demodulator and the decimation filter using pipeline interleaving (PI) technique. The pipeline interleaving technique introduces the efficient architecture [9]. Furthermore, since it is not necessary to use a MUX at the output of the second stage, the proposed two-stage digital I/Q demodulator is suitable for the decimation section which adopts the pipeline interleaving structure.…”

Section: X(t) Is the Bandpass If Signal A(t) Is The Amplitude Of X(tmentioning

confidence: 99%

Two-stage digital I/Q demodulator employing a reconfigurable 16-phase down-mixing technique

Jeong

Min

Kim

2010

IEICE Electron. Express

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This letter presents a new two-stage digital I/Q demodulator employing a reconfigurable 16-phase quadrature intermediate frequency (IF) sampling technique for multistandard wireless systems such as mobile TV applications. The proposed two-stage digital I/Q demodulator provides the flexibility for the multiphase scheme such as a quadrature phase shift keying (QPSK) and 16-quadrature amplitude modulation (QAM) at the level of down-mixing, which introduces an efficient architecture for the following decimation filter. In this letter, the prototype chip has been implemented in a 0.18 μm standard CMOS technology and occupied with the active chip area of 0.02 mm 2 . The power consumption of the fabricated chip is 0.42 mW with a 1.8 V supply voltage at the sampling frequency of 26 MHz. The experimental results show that the proposed two-stage digital I/Q demodulator is suitable for multistandard wireless systems which require small silicon area and low power dissipation.

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Section: X(t) Is the Bandpass If Signal A(t) Is The Amplitude Of X(tmentioning

confidence: 99%

Two-stage digital I/Q demodulator employing a reconfigurable 16-phase down-mixing technique

Jeong

Min

Kim

2010

IEICE Electron. Express

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“…Therefore a trade off between number of stages and complexity must be achieved [1], [14]. The efficient decomposition proposed in [2], [3], are showed in the table I.…”

Section: A Decimation Factor Decompositionmentioning

confidence: 99%

“…Therefore, Pipeline/Interleaving architectures will reduce these parameters by using an expanded filter to process two different signals [4]. Figure 1 shows a general proposed architecture where CIC filters are used in each branch [2], [3]. Therefore, this structure continues working smoothly as high performance architecture with few filter blocks to switch between different communication standards.…”

Section: Common Blocksmentioning

confidence: 99%

“…The most expensive block on downconverters is the decimator filter, which realizes the sample rate conversion from intermediate frequency (IF) to baseband frequency [8], [9]. Different approaches obtaining efficient and flexible decimation filters, as part of multi-standard digital receivers, have been proposed by [2], [3], [10], and [11]. The architecture based on Pipeline/Interleaving (PI) using Finite Impulse Response (FIR) filters obtains remarkable results compared with previous works.…”

Section: Introductionmentioning

confidence: 99%

“…The architecture based on Pipeline/Interleaving (PI) using Finite Impulse Response (FIR) filters obtains remarkable results compared with previous works. We propose to use infinite impulse response (IIR) filters to reduce the multiplications on each stage of PI architectures proposed in [2], [3].…”

Section: Introductionmentioning

confidence: 99%

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Low Complexity Decimation Filter for Multi-Standard Digital Receivers

Tecpanecatl-Xihuitl

Kumar

Bayoumi

2005 IEEE International Symposium on Circuits and Systems

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This paper proposes a reduction in complexity of decimation filter architectures used in multi-standard digital receiver, using IIR filters implemented as a sum of two all-pass filters. The decimation filters are an important block in devices, which want to establish communication using different standards. IIR filters are implemented on specific stages of multistage Pipeline/Interleaving structure, where high order of filters is power consuming and area demanding. Therefore, a major reduction in complexity is obtained. Regularity is an important property of all pass filters, which can be decomposed on first or second order all-pass transfer functions achieving more efficient implementation. The results presented are implemented in Pipeline/Interleaving architectures using specific decimation decomposition proposed previously [2], [3]. Reductions of 36%, 77%, and 80% are obtained compared with previous works, where basically these implementations are based on linear phase filters. The decimation filter architecture is simulated using Matlab.

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Efficient multistage decimation filter using pipeline/interleaving architectures for digital IF receiver

Cited by 2 publications

References 2 publications

Two-stage digital I/Q demodulator employing a reconfigurable 16-phase down-mixing technique

Two-stage digital I/Q demodulator employing a reconfigurable 16-phase down-mixing technique

Low Complexity Decimation Filter for Multi-Standard Digital Receivers

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