With the decrease in device feature sizes, planarization of both front-and back-end layers by the chemical-mechanical planarization (CMP) process has become necessary for integrated circuit (IC) fabrication technologies smaller than 0.35 mm. As much as the industry has benefitted tremendously from the introduction and implementation of CMP, the very process has also brought along a set of new challenges to the fabs. For example, surface defects or imperfections such as leftover particles, organic residues, metallic contaminations, scratches, and corrosion spots can often be found on the polished wafers after the CMP process. These CMP-induced defects can arise from the slurries, the polishing pad, the pad conditioner, and to a lesser extent, the polisher. The leftover particles can physically attach to the wafer surface or, in the worst case, even partially embed into the top layer of a wafer. The CMP process can also leave metallic contamination typically in the range of 10 11 -10 12 atoms/ cm 2 . These contaminants mainly arise from the abraded metal lines, metal ions in the slurries, and polishers. In front-end applications such as a shallow trench isolation (STI) process, the control of metallic contamination levels is very critical because the following high-temperature process may lead to a complete incorporation of the metal ions into the lattice. In the case of back-end processes, if not removed, these metal contaminants can lower the breakdown voltage of devices. Also, fast diffusers such as copper can reach the active area from the backside surface or edge during the following thermal process [1]. During CMP, slurry additives and pad debris can leave organic residues on the Microelectronic Applications of Chemical Mechanical Planarization, Edited by Yuzhuo Li
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