This work investigates a post-CMOS (complementary metal-oxide semiconductor) bulk micromachining process for fabricating suspended microstructures. The advantage of the post-CMOS process is easy execution with low-cost maskless wet etching. The post-CMOS process involves wet etching to remove sacrificial layers, which are stacked layers formed from metal and via layers, to expose the silicon substrate. Then, KOH solution is employed to etch the silicon substrate to develop deep cavities and generate suspended structures. Many suspended structures, which include bridges and plates, are fabricated using the post-CMOS bulk micromachining process. With the same process, two devices that are a suspended micro inductor and a micro hot plate are manufactured successfully. Experimental results reveal that the maximum quality factor of the suspended micro inductor is 4.8 at 4 GHz, and the micro hot plate can generate a high temperature of 300 °C with an applied voltage of 4 V, which has excellent thermal isolation and heating effect.

Packaging is a core technology for the advancement of microelectromechanical systems (MEMS) and nanoelectromechanical systems (NEMS). We discuss MEMS packaging challenges in the context of functional interfaces, reliability, modeling and integration. These challenges are application-dependent; therefore, two case studies on accelerometers and BioMEMS are presented for an in-depth illustration. Presently, most NEMS are in the exploratory stage and hence a unique path to identify the relevant packaging issues for these devices has not been determined. We do, however, expect the self-assembly of nano-devices to play a key role in NEMS packaging. We demonstrate this point in two case studies, one on a silicon nanowire biosensor, and the other on self-assembly in molecular biology. MEMS/NEMS have the potential to have a tremendous impact on various sectors such as automotive, aerospace, heavy duty applications, and health care. Packaging engineers have an opportunity to make this impact a reality by developing low-cost, high-performance and high-reliability packaging solutions.

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Thermal hysteresis reduction is usually a difficult task to tackle for micromachined pressure sensors especially when shrinking the piezoresistive transducer (PRT) sensing element. Since thermal hysteresis involves the entire thermal cycling history and complicated material properties varied with temperatures, viscoplastic deformation makes the problem very complicated when dealing with high-precision sensor signals. The approach to simplify and quickly resolve the thermal hysteresis problem is the key methodology proposed by this paper. The objective of this project is to optimize the metal layout design on the sensing element and lower down the thermal hysteresis. It is time consuming and cost ineffective to rely purely on the hardware tests to solve the thermal hysteresis problem. ANSYS is used to predict the shear stress at the transducer location and the phenomenological theory of silicon piezoresistance is used to calculate the output voltage and thermal hysteresis. The element-death-and-birth technique is used to simulate the bonding process at various temperature levels for the sensing element packaging. With the aid of the finite element analysis (FEA) tool, the PRT sensing element design was quickly optimized and product development cycle time was reduced.

A capacitive micropressure sensor with readout circuits on a single chip is fabricated using commercial 0.35 mum complementary metal oxide semiconductor (CMOS) process and post-processing. The main break through feature of the chip is the positioning of its readout circuits under the pressure sensor, allowing the chip to be smaller. Post-processing included anisotropic dry etching and, wet etching to remove the sacrificial layer, and the use of plasma enhanced chemical vapor deposition (PECVD) of nitride to seal the etching holes on the pressure sensor. The readout circuit is divided into analog and digital parts, with the digital part being an alternate coupled RS flip-flop with four inverters that sharpened the output wave. The analog part employed switched capacitor methodology. The pressure sensor contained an 8x8 sensing cells array, and the total area of the pressure sensor chip is 2mmx2mm