Abstract-Many integrated circuit systems, particularly in the multimedia and telecom domains, are inherently data dominant. For this class of systems, a large part of the power consumption is due to the data storage and data transfer. Moreover, a significant part of the chip area is occupied by memory. The computation of the memory size is an important step in the system-level exploration, in the early stage of designing an optimized (for area and/or power) memory architecture for this class of systems. This paper presents a novel nonscalar approach for computing exactly the minimum size of the data memory for high-level procedural specifications of multidimensional signal processing applications. In contrast with all the previous works which are estimation methods, this approach can perform exact memory computations even for applications with numerous and complex array references, and also with large numbers of scalars.
In real-time multimedia processing systems a very large part of the power consumption is due to the data storage and data transfer. Moreover, the area cost is often largely dominated by the memory modules. The computation of the memory size is an important step in the process of designing an optimized (for area and/or power) memory architecture for multimedia processing systems. This paper presents a novel non-scalar approach for computing exactly the memory size in real-time multimedia algorithms. This methodology uses both algebraic techniques specific to the data-flow analysis used in modern compilers, and also recent advances in the theory of integral polyhedra. In contrast with all the previous works which are only estimation methods, this approach performs exact memory computations even for applications with a large number of scalar signals.
-In real-time data-dominated communication and multimedia processing applications, due to the manipulation of large sets of data, a multi-layer memory hierarchy is used to enhance the system performance and also to reduce the energy consumption. Savings of dynamic energy can be obtained by accessing frequently used data from smaller memories rather than from large background memories. The optimization of the hierarchical memory architecture implies the addition of layers of smaller memories to which heavily used data can be copied. This paper presents a formal model for data reuse analysis which identifies those parts of arrays more intensely accessed, taking also into account the relative lifetimes of the signals. Tested on a two-layer memory hierarchy, this model led to savings in the dynamic energy from 40% to over 70% relative to the energy used in the case of a flat memory design.
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