We studied the diffusion of impurities in dual polysilicon gates, and found that this phenomenon can effectively be treated as diffusion from a constant concentration diffusion source for both p+ and n+ polysilicon gates. We derived a model for the critical time required to obtain a flat profile. We then clarified the thermal budget required for suppressing gate depletion and impurity penetration through a gate oxide. According to our study, the thermal budget for n-type metal-oxide-semiconductor-field-effect-transistor (MOSFET) is always wider than that for p-type MOSFET, and the budget for p-type MOSFET is wide enough for realizing a flat profile without impurity penetration using pure SiO2 if B is available instead of BF2.
We found that B diffusion profiles in polysilicon can be regarded as having a constant surface concentration, N 0. Using this finding, we derived a B diffusion profile model and identified the diffusion coefficient of B in polysilicon. We also derived the model for the critical time, tl, to flatten the B profile in a polysilicon gate. Using the critical time for B penetration through the gate oxide, t2, we determined the allowable diffusion time t as tl < t < tz. We showed that B implantation provides a thermal budget wide enough to fabricate p+ polysiticon gates for 0.1 ~m complementary metal oxide semiconductor with pure SiO2.
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