At present power DMOS transistors are regarded as one ofthe most prospective componentsfor many power-saving devices. When developing power DMOS transistors, which parameters are analogs ofIRL 640, "Transistor Factory " ofRPC "Integral " used the skills ofphysical and layout simulation and design of low-power LSI having N-channel MOS transistor structures. Based on this approach and using the developed original software, conducted was optimization ofparameters ofsolid-state structure ofpower DMOS transistors ofKP728E] type. In particular, minimized were the resistance values between the drain and source areas in the transistor "open " state, output andpass-by capacitances ofcell transistor structure when maintaining other parameters at the set level. Given are resistive and capacitance models ofa DMOS transistor. Resistance ofa conductive channel in an elementary cell ofa DMOS transistor was calculated as the sum ofcapacitances ofa solid-state structure, including herein the induced channel ofa horizontal N-MOS transistor, and the cell's capacitances are optimized taking into account SiO2 thickness in different parts ofthe structure.
An approach to screening of ICs and discrete transistors for ESD susceptibility is discussed. Procedures are proposed for comparing transistor batches in terms of reliability and for identifying items of unusual reliability among conforming ones in an IC batch, using annealing of ESD-induced faults.
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