Transparent nanofloating gate memory devices based on top-gate zinc oxide thin-film transistors were developed. The proposed devices contained a facile and dry-synthesized palladium nanocluster array as a charge-trapping layer. The good programmable memory characteristics were exhibited due to the thin tunneling oxide, caused by the top-gate structure. The good endurance, data retention capability, and environmental stability demonstrated by the proposed device made it suitable for nonvolatile memory applications. As the whole processes were carried at room temperature, this letter has a potential use in fabricating high-performance and high-reliability nonvolatile memory devices on flexible substrates.
We have fabricated Si(1-x)Ge(x) alloy nanowire devices with Ni and Ni/Au electrodes. The electrical transport characteristics of the alloy nanowires depended strongly on the annealing temperature and contact metals. Ni/Au-contacted devices annealed at 400 degrees C showed p-type transistor behavior as well as a resistance switching effect, while no switching was observed from Ni-contacted alloy nanowire devices. To identify the origin of such a hysteretic resistance switching effect, we constructed nanowire devices on a 40 nm Si(3)N(4) membrane. Transmission electron microscopy analysis combined with electrical transport measurements revealed that devices contacted with Ni/Au, and thereby showing resistance switching, have Au atoms right next to the alloy nanowire.
Metal nanoclusters were fabricated by inert-gas condensation in a sputtering reactor. From transmission electron microscopy, it was confirmed that copper nanoclusters with a high degree of monodispersity in size of about 5 nm were successfully produced. The conductance of the percolated nanocluster film was measured. In order to incorporate nano-scale arrangement characterizations in nano-devices being operated in air, aging experiments of the specimen after long time in air were carried. Negative temperature coefficient of resistance suggests that surface native copper oxide in core-shell structured nanoclusters was mainly responsible for the conductance, because copper oxide is known as semiconductor. After aged at higher than 100 degrees C, the conductance at room temperature didn't return to the original value. This irreversible phenomenon might be due to coarsening and/or coalescence of copper nanoclusters.
A metal-induced laterally crystallized silicon thin-film transistor (TFT) with an asymmetric-channel dual-gate structure was fabricated and characterized. It features a sub-TFT near the drain with multichannel consisting of narrower unit channel width, resulting in higher field-effect mobility compared to a sub-TFT near the source with single-channel. The proposed TFT effectively suppressed the kink current with a field-effect mobility to be almost on a level with the conventional single-gate TFT. This improvement was explained by measurement of floating voltages revealing that the sub-TFT near the source of the proposed TFT operates in the near saturation regime under high drain voltages.
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