High-performance and room-temperature-processed nanofloating gate memory devices based on top-gate transparent thin-film transistors

Abstract

Transparent nanofloating gate memory devices based on top-gate zinc oxide thin-film transistors were developed. The proposed devices contained a facile and dry-synthesized palladium nanocluster array as a charge-trapping layer. The good programmable memory characteristics were exhibited due to the thin tunneling oxide, caused by the top-gate structure. The good endurance, data retention capability, and environmental stability demonstrated by the proposed device made it suitable for nonvolatile memory applications. As the whole processes were carried at room temperature, this letter has a potential use in fabricating high-performance and high-reliability nonvolatile memory devices on flexible substrates.

High-performance transparent, all-oxide nonvolatile charge trap memory transistor using In-Ga-Zn-O channel and ZnO trap layer

“…The influences of gate-stack structures and employed materials on memory behavior also have been widely characterized. [3][4][5][6][7][8][9][10][11][12] However, there still remain some critical limitations for OxCTMTs, such as a relatively long program time and an insufficient retention period for practical memory applications. To mitigate these issues and to achieve Ox-CTMTs with transparent gate-stack structures, the composition and thickness values of the gate-stack materials must be carefully optimized.…”

Effects of thickness and geometric variations in the oxide gate stack on the nonvolatile memory behaviors of charge-trap memory thin-film transistors

“…Charge-trap memory thin-film transistors (CTM-TFTs) with oxide semiconductor channels have been actively investigated using various types of charge-trap (CT) materials including metal nanoparticles [1][2][3], Si-based insulators [4][5][6], high-k dielectrics [7,8], and oxide semiconductors [9,10] in an attempt to enhance the overall memory behavior. The CT layers employed in CTM-TFTs play important roles in determining the efficiency of charge-trap and de-trap events.…”

The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET

“…In the floating-gate transistor, the charges in the substrate region are stored in the floating-gate region by the Fowler-Nordheim tunneling. And the reading operation depends on the thermionic emission [ 5 , 6 ], which is the same as the metal-oxide-semiconductor field-effect transistor (MOSFET). As a result, the reading current of the DRAM with the floating-gate transistor has a strong dependence on the temperature.…”