The reduction in current ability accompanied by the hump phenomenon in oxide semiconductor thin-film transistors to which high DC voltages and AC drive voltages are applied has not been studied extensively, although it is a significant bottleneck in the manufacture of integrated circuits. Here, we report on the origin of the hump and current drop in reliability tests caused by the degradation in the oxide semiconductor during a circuit driving test. The hump phenomenon and current drop according to two different driving stresses were verified. Through a numerical computational simulation, we confirmed that this issue can be caused by an additional “
needle
”, a shallow (~0.2 eV) and narrow (<0.1 eV), defect state near the conduction band minimum (CBM). This is also discussed in terms of the dual current path caused by leakage current in the channel edge.
Cu/low-k dielectrics are required to reduce resistance-capacitance (RC) delay and parasitic capacitance at the back-end-of-line (BEOL) interconnection. Integration of Cu/low-k dielectrics (black diamond) for BEOL interconnection in 0.13μm technology has gained wide acceptance in the microelectronics industry in recent years. In this article, the authors discuss the process-integration issues of 0.13μm Cu/low-k dual-damascene integration for static random access memory (SRAM) device yield. The same scheme of 0.13μm Cu/fluorinated silicate glass–based device was used for the full process of making a low-k based device. Black diamond was used as a low-k material with a dielectric constant of 2.95. To reduce the damage of low-k and improve the yield of a low-k based device, H2O ashing, organic cleaning, and reduced down pressure in chemical-mechanical planarization were selected for the study. Specifically, the cleaning process after the ashing process was very effective for the removal of organic residues from via, trench, and surface contaminants. There was an increase of 40.79% in SRAM device yield compared to the low-k based device without the organic cleaning chemical process. As a result, the authors successfully integrated a 0.13μm Cu/low-k dual-damascene interconnection with excellent yield performance after the improving process of organic cleaning.
This article deals with a novel 3-D sensor system that employs a measurement technique called the Stereo Moiré technique. The general Moiré method, which is well known for fast and accurate 3-D measurement, has suffered from an inherent limitation in that it cannot measure the absolute 3-D depth due to 2p ambiguity caused by regularity of fringe. In this article, to overcome this 2p ambiguity and obtain the exact depth value effectively, a novel method is proposed. The measurement system consists of a digital pattern projector and two cameras, which can indirectly detect two phase information on the fringe patterns projected onto an object's surface. These two phase values are different due to the difference in camera position. However, the depth values obtained at two different phase information must be identical because the two cameras look at the same point on the object being measured. To verify the efficiency and accuracy of the proposed method, a series of experimental tests was performed. Through the experiments, it is shown that the proposed method can effectively overcome the 2p ambiguity of the typical Moiré technique, and obtain the absolute depth value of the 3-D scene geometric information with satisfactory accuracy.
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