Morphologically driven dynamic wickability is essential for determining the hydrodynamic status of solid-liquid interface. We demonstrate that the dynamic wicking can play an integral role in supplying and propagating liquid through the interface, and govern the critical heat flux (CHF) against surface dry-out during boiling heat transfer. For the quantitative control of wicking, we manipulate the characteristic lengths of hexagonally arranged nanopillars within sub-micron range through nanosphere lithography combined with top-down metal-assisted chemical etching. Strong hemi-wicking over the manipulated interface (i.e., wicking coefficients) of 1.28 mm/s0.5 leads to 164% improvement of CHF compared to no wicking. As a theoretical guideline, our wickability-CHF model can make a perfect agreement with improved CHF, which cannot be predicted by the classic models pertaining to just wettability and roughness effects, independently.
Active modulation of ions and molecules via field-effect gating in nanofluidic channels is a crucial technology for various promising applications such as DNA sequencing, drug delivery, desalination, and energy conversion. Developing a rapid and facile fabrication method for ionic field-effect transistors (FET) over a large area may offer exciting opportunities for both fundamental research and innovative applications. Here, we report a rapid, cost-effective route for the fabrication of large-scale nanofluidic field-effect transistors using a simple, lithography-free two-step fabrication process that consists of sputtering and barrier-type anodization. A robust alumina gate dielectric layer, which is formed by anodizing sputtered aluminium, can be rapidly fabricated in the order of minutes. When anodizing aluminium, we employ a hemispherical counter electrode in order to give a uniform electric field that encompasses the whole sputtered aluminium layer which has high surface roughness. In consequence, a well-defined thin layer of alumina with perfect step coverage is formed on a highly rough aluminium surface. A gate-all-around nanofluidic FET with a leak-free gate dielectric exhibits outstanding gating performance despite a large channel size. The thin and robust anodized alumina gate dielectric plays a crucial role in achieving such excellent capacitive coupling. The combination of a gate-all-around structure with a leak-free gate dielectric over a large area could yield breakthroughs in areas ranging from biotechnology to energy and environmental applications.
We report combined electrochemical double-layer capacitance (EDLC) and pseudocapacitance in reduced graphene oxide (rGO) thick film like paper due to annealing temperature variations. The influence of annealing temperature (from room temperature (RT) to 1000 C) on the structural, morphological, electrical, and electrochemical properties of rGO paper was evaluated. Upon increasing the annealing temperature, shifting of the dominant (002) X-ray diffraction (XRD) peak to a higher degree, volume expansion, and red-shifting of the G band in Raman spectra were observed. High-resolution transmission electron microscopy (HRTEM) images showed a reduction in the interlayer distance in rGO sheets from 0.369 to 0.349 nm as the annealing temperature increased from RT to 1000 C; these results were congruent with the XRD results. According to X-ray photoelectron spectroscopy (XPS), the presence of hydroxyl, carboxyl, and other oxygen-containing groups decreased in samples annealed at higher temperatures. The attached functional groups, the electrical conductivity, and the supercapacitance of rGO papers were found to be mutually interrelated and could be tuned by varying the annealing temperature. The rGO paper annealed at 200 C in a 1 M H 2 SO 4 electrolyte at a scan rate of 50 mV s À1 exhibited a maximum specific capacitance of 198 F g À1 .
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