Abstract-This paper presents a fully pipelined color demosaicking design. To improve the quality of reconstructed images, a linear deviation compensation scheme was created to increase the correlation between the interpolated and neighboring pixels. Furthermore, immediately interpolated green color pixels are first to be used in hardware-oriented color demosaicking algorithms, which efficiently promoted the quality of the reconstructed image. A boundary detector and boundary mirror machine were added to improve the quality of pixels located in boundaries. In addition, a hardware sharing technique was used to reduce the hardware costs of three interpolators. The VLSI architecture in this work contains only 4.97 K gate counts and the core area is 60,229 um 2 synthesized by using 0.18-um CMOS process. The operating frequency of this work is 200 MHz by consuming 4.76 mW. Compared with the previous lowcomplexity designs, this work has the benefits in terms of low cost, low power consumption, and high performance.
A novel low-complexity and high-quality colour demosaicking algorithm is proposed for very large-scale integration (VLSI) implementation for real-time video applications. It consists of a boundary detector, a boundary mirror model and five green and red-blue colour interpolation models. Two of the five interpolation models can be selected adaptively according to boundary and position information. In addition, a boundary mirror machine and identical direction technique were used to improve the qualities of the reconstructed images. To reduce the hardware cost, memory requirement and power consumption, a hardware-sharing technique and register bank design were used to realise the proposed algorithm. The VLSI architecture of this work contains only 2.9 K gate counts and its core area is 35 966 μm 2 synthesised by a 0.18 μm CMOS process. The synthesised results show that this design performs an operating frequency of 100 MHz processing rate by consuming only 1.83 mW. Compared with the previous low-complexity designs, this work not only reduces at least 48.2% of gate counts and 96.7% of power consumption but also improves the average CPSNR quality by more than 0.78 dB.Introduction: Recently, with the rapid development of portable consumer electronic products, such as smart phones, tablet PCs, digital cameras, digital video etc., the usage and applications of digital cameras have become increasingly wider. Since the general optical lens can only capture one component colour of red, green and blue (RGB), the colour filter array (CFA) format is popular in digital cameras. Although the storage of the captured images in the CFA format can be greatly reduced, it causes distortion because two-thirds of colour pixels are missed. Thus, it is necessary to develop colour demosaicking algorithms to reconstruct a full RGB complete image from an image in the CFA format. For this reason, an optimal integer finite impulse response filter algorithm was proposed for colour interpolation [1]. This had the advantages of high-quality and easy development for hardware implementation. Su and Lin [2] presented a wavelet-based classifiers algorithm for colour interpolation. Although the quality of reconstructed images can be greatly improved by predicting the preferred direction of the missed green pixels, it is not easy to implement their algorithm by using the very large-scale integration (VLSI) technique for video applications. Shia et al. proposed two hardware-oriented colour demosaicking algorithms [3, 4] by using edge weights, colour correction, colour space conversion, automatic gain control and colour enhancement techniques. Two efficient VLSI architectures were realised by using pipeline and hardware-sharing schemes. However, the chip areas of these designs are limited by using dividers and multipliers. Recently, Shiau et al.[5] proposed a costefficient algorithm by using edge-information and inter-channel correlation techniques. This study provided a low-cost hardware architecture because the algorithm only included addition, subtra...
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