Abstract

A novel lateral IGBT with a second gate on the emitter portion is presented. A PMOS transistor, driven by the proposed device itself, is used to short the PN junction at the emitter while turned off. Low on state voltage and fast turn off speed are obtained without side-effects such as snapback I -V characteristics and difficulties of process complexity. Numerical simulation results show a drop of fall time from 120 to 12 ns and no increase of on state voltage.

This paper proposes an innovative methodology to design a DSP (Digital Signal Processing) system using FPGA (Field-programmable Gate Array). There are several main components in this system, including A/D sampling unit, FFT processing unit and control unit. A/D sampling and FFT processing units utilize the Nios processor in FPGA as controller. Control unit uses EP1C20 FPGA chip from ALTERA as FFT processing unit so as to manage the FIFO operations. This unit can handle 128 FFT operations. This system design approach is tested on Matlab. The results indicate that the calculation speed is much faster than common DSP manner.

When displaying Standard Dynamic Range (SDR) video on High Dynamic Range (HDR) displays a reverse tone mapping operation can be employed to expand the dynamic range of the SDR video to that offered by the display. This paper presents a subjective performance evaluation of existing reverse Tone Mapping Operators (rTMOs). The presented study evaluates the performance of rTMOs acting on both well exposed SDR video and video that exhibits exposure variation, as is often the case with user generated content (e.g. captured on mobile phones). The paper highlights flickering artefacts that arise in such cases and evaluates the effect on perceived quality of an adapted de-flickering method.

No abstract