This paper presents a multiphase-output delay-locked loop (MODLL). The proposed phase/frequency detector (PFD) utilizes a new NAND-resettable dynamic D-flip-flop (DFF) circuit to achieve a shorter reset path. Thus, lower power consumption and higher speed can be obtained. The proposed voltage-controlled delay element used in this design can operate at a lower supply voltage and overcome the dead-band issue of the voltage-controlled delay line. An experimental multiphase-output DLL was designed and fabricated using a TSMC 0.35-mu m 2P4M CMOS process. The delay-locked loop (DLL) power consumption is 3.4 mW with a 2 V supply and a 100 MHz input. The measured rms and peak-to-peak jitters are 17.575 ps and 145 ps, respectively. In addition, the supply voltage of the experimental multiphase-output DLL can vary from 1.5 V to 2.5 V without causing malfunctions. The active area is 426 mu m x 381 mu m
In this study, a precision bandgap reference with a v-curve correction (VCC) circuit is presented. The proposed VCC circuit generates a correction voltage to reduce the temperature drift of the reference voltage and achieves a low temperature coefficient (TC) in a wide temperature range. The proposed bandgap reference was designed and fabricated using a standard TSMC 0.18-µm 1P6M CMOS technology with an active area of 0.0139 mm 2. The measured results show that the proposed bandgap reference achieves a TC of 1.9-5.28 ppm/ • C over a temperature range of −40 • C to 140 • C at a supply voltage of 1.8 V. In addition, the circuit demonstrated a line regulation of 0.033 %/V for supply voltages of 1.2-1.8 V at room temperature.
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