The characteristics of electroless copper plating on different substrates of TiN/SiO 2 /Si, Cu seed /Ta/SiO 2 /Si, and Cu seed /TaN/SiO 2 /Si have been investigated. Continuous copper films with good surface morphology are obtained, and hydrogen-induced blister formation is inhibited by optimizing plating solution and conditions. Surface roughness of the electrolessly plated copper films increases with increasing film thickness, and the average roughness is 11 nm at a film thickness of 1 m on Cu seed /TaN/SiO 2 /Si substrate. Conformal copper deposition with excellent step coverage completely fills deep subquarter-micrometer features of high aspect ratios up to five. Copper growth orientation depends on the underlayer structure. A copper film with strong (111) texture is plated on the (111) textured copper seed layer of Cu seed /TaN/SiO 2 /Si substrate, while no preferred orientation is found on the other substrates. After thermal annealing at 400ЊC in N 2 /H 2 for 1 h, Cu(111) texture is enhanced in all systems. By thermal annealing, defects in the plated copper are reduced, and the electrical resistivity of the plated copper is lowered to 1.75 ⍀ cm at room temperature.

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An electrochemical deposition process for copper ͑Cu͒ metallization has been developed and investigated by the integration of nanoscaled palladium ͑Pd͒ catalyzation, electroless plating of Cu seed layers, and electroplating of Cu films in this study. Following surface cleaning and etching, sensitization and activation of Si/SiO 2 /TaN substrates were performed to obtain uniformly distributed Pd catalysts of only about 10 nm. Smooth and continuous 30 nm thick Cu seed layers with low electrical resistivity were electrolessly deposited using the nanosized Pd catalysts as nucleation sites. Copper metallization with high purity, small surface roughness, low electrical resistivity of 1.77 ⍀ cm, low residual stresses, and good adhesion to substrates was achieved using the subsequent electroplating on the electroless seed layers and postannealing. Good gap-filling capability on finely patterned structures was performed and exhibited the great application potential of low-temperature integrated electrochemical deposition process for next-generation Cu metallization of ultralarge-scale integrated circuits.As the packing density of semiconductor devices drastically increases, multilevel interconnection has been applied to compromise the insufficient surface area on integrated circuit ͑IC͒ chips. At the same time, the reduction in metal linewidths and pitches results in the rise of interconnect resistance and parasitic capacitance, leading to serious resistance-capacitance ͑RC͒ delay. 1,2 The RC delay has many drawbacks, especially the problem of low signal transmission speed, becoming the most difficult issue to overcome. Copper with lower electrical resistivity, high thermal conductivity, good mechanical properties, and high migration resistance has been used as interconnect metallization in dual-damascene structures of ultralargescale integrated ͑ULSI͒ circuits to replace aluminum and to directly reduce the metal line resistance. [3][4][5] Copper metallization technology mainly includes traditional ULSI techniques such as physical vapor deposition ͑PVD͒ and chemical vapor deposition ͑CVD͒, or newly developed electrochemical deposition including electroplating and electroless plating. 6-23 The PVD method provides precise composition control but presents poor step coverage in deep submicrometer dimension features, resulting in problems like overhangs or voids. 6-8 Though CVD has better step coverage, its development is also limited because high processing temperatures and expensive equipment are required in addition to the combustible and toxic precursors. 9,10 Electroplating has the advantages of low processing temperature, low cost, high throughput, and good film quality, and thus becomes more attractive. 3,11-15 However, due to the need of sputtered Cu seed layers for electroplating, this deposition technique is inadequate for next-generation metallization below 90 nm. Recently, the deposition of uniform Cu seed layers only 20 nm thick into trenches or vias with good sidewall step coverage and a high aspect ratio of 10 h...

The catalyzation of TaN/SiO 2 /Si substrates was carried out by immersion in SnCl 2 /HCl and PdCl 2 /HCl solutions for electroless Cu deposition. The sizes and morphologies of the catalytic sites on the TaN layers were found to be a function of catalyzation conditions, including solution temperature, immersion time, and the surface oxides. The appropriate formula for catalyzation was obtained by considering both the quality and efficiency. The catalytic sites were composed of Sn and Pd, and the ratio of Sn/Pd was about 1.3. During electroless Cu deposition on the catalyzed TaN/SiO 2 /Si substrates, Cu nuclei first formed at the catalytic sites in the early stage, gradually agglomerated into dense islands, and finally merged to continuous deposition films. The Cu films were uniformly and smoothly deposited with a surface roughness of 6.2 nm under a film thickness of 210 nm. The lowest electrical resistivity of the Cu films was 2.5 ⍀ cm, and the residual resistivity contributed to the participation of Sn-Pd catalyst and internal defects. Good gap-filling capability of electroless Cu deposition on Sn/Pd catalyzed, patterned substrates exhibited its high potential to act as a seed layer for Cu electrodeposition and even to completely fill submicrometer gaps in ultralarge-scale integrated metallization.Metallization is a critical issue in the production of ultralargescale integrated ͑ULSI͒ circuits. As the size of the devices scales down and chip density highly increases, copper ͑Cu͒ has been proposed as the most reliable interconnect material to replace aluminum because of its significant advantages of low electrical resistivity, low power dissipation, and high resistance to electromigration. 1,2 Recently, Cu deposition by electrochemical methods has received great attention, since high-quality Cu films can be easily obtained at a low deposition temperature and by low tool cost. 3,4 Electroless copper deposition has excellent step-coverage capability for high-aspectratio ͑A.R.͒ gaps and can be used either to produce the seed layer for copper electrodeposition or to fill the fine gaps directly. 5-7 Besides, due to the high selectivity, the low processing temperatures, the low cost of raw materials and equipment, and the feasibility, 8 it becomes attractive and is under continuous investigation.However, some problems associated with Cu metallization must be solved, especially, the easy diffusion of Cu into SiO 2 and Si and its poor adhesion to dielectric layers. Therefore, for the successful integration of Cu metallization with integrated circuit ͑IC͒ processes, proper diffusion barrier layers of refractory metals and their nitrides are required to be placed between Cu and either the dielectric layers or the Si substrate to prevent the diffusion of Cu and to improve interfacial adhesion. Tantalum nitride ͑TaN͒, recognized as one of the most promising diffusion barriers for Cu, not only provides high thermal stability, but also has characteristics such as acceptable conductivity and the chemical inactivity with Cu. 9,10...