Integrated Electrochemical Deposition of Copper Metallization for Ultralarge-Scale Integrated Circuits

Abstract

An electrochemical deposition process for copper ͑Cu͒ metallization has been developed and investigated by the integration of nanoscaled palladium ͑Pd͒ catalyzation, electroless plating of Cu seed layers, and electroplating of Cu films in this study. Following surface cleaning and etching, sensitization and activation of Si/SiO 2 /TaN substrates were performed to obtain uniformly distributed Pd catalysts of only about 10 nm. Smooth and continuous 30 nm thick Cu seed layers with low electrical resistivity were electrolessly deposited using the nanosized Pd catalysts as nucleation sites. Copper metallization with high purity, small surface roughness, low electrical resistivity of 1.77 ⍀ cm, low residual stresses, and good adhesion to substrates was achieved using the subsequent electroplating on the electroless seed layers and postannealing. Good gap-filling capability on finely patterned structures was performed and exhibited the great application potential of low-temperature integrated electrochemical deposition process for next-generation Cu metallization of ultralarge-scale integrated circuits.As the packing density of semiconductor devices drastically increases, multilevel interconnection has been applied to compromise the insufficient surface area on integrated circuit ͑IC͒ chips. At the same time, the reduction in metal linewidths and pitches results in the rise of interconnect resistance and parasitic capacitance, leading to serious resistance-capacitance ͑RC͒ delay. 1,2 The RC delay has many drawbacks, especially the problem of low signal transmission speed, becoming the most difficult issue to overcome. Copper with lower electrical resistivity, high thermal conductivity, good mechanical properties, and high migration resistance has been used as interconnect metallization in dual-damascene structures of ultralargescale integrated ͑ULSI͒ circuits to replace aluminum and to directly reduce the metal line resistance. [3][4][5] Copper metallization technology mainly includes traditional ULSI techniques such as physical vapor deposition ͑PVD͒ and chemical vapor deposition ͑CVD͒, or newly developed electrochemical deposition including electroplating and electroless plating. 6-23 The PVD method provides precise composition control but presents poor step coverage in deep submicrometer dimension features, resulting in problems like overhangs or voids. 6-8 Though CVD has better step coverage, its development is also limited because high processing temperatures and expensive equipment are required in addition to the combustible and toxic precursors. 9,10 Electroplating has the advantages of low processing temperature, low cost, high throughput, and good film quality, and thus becomes more attractive. 3,11-15 However, due to the need of sputtered Cu seed layers for electroplating, this deposition technique is inadequate for next-generation metallization below 90 nm. Recently, the deposition of uniform Cu seed layers only 20 nm thick into trenches or vias with good sidewall step coverage and a high aspect ratio of 10 h...

Grain size effect on nanomechanical properties and deformation behavior of copper under nanoindentation test

“…For electrochemically deposited high-purity copper ͑Cu͒ films, which have been widely adopted as a multilevel interconnect metallization in ultralarge-scale integrated ͑ULSI͒ circuits, [9][10][11][12][13][14] mechanical damages to these films caused by thermal stresses and chemical-mechanical polishing severely suppress the processing yield and application reliability of integrated circuits. [15][16][17][18] Especially, electrolessly deposited Cu films, intensively studied as a potential Cu metallization in finely patterned features below 90 nm, [10][11][12][13][14] are reported to possess ultrafine grains sizes Ͻ10 nm.…”

Electroless- and Electroplating of Cu(Re) Alloy Films for Self-Forming Ultrathin Re Diffusion Barrier

“…26,27 A pure Cu or a Cu(Re) alloy film of about 150 nm thick was deposited on the catalyzed substrates in an EL Cu or EL Cu(Re) solution, as listed in Table I, at 50-60…”

“…[26][27][28] Three mixed solutions with different EL Cu and EL Re composition ratios (EL Cu: EL Re = 10:1, 10:2 and 10:3) were attempted for the EL Cu(Re) depositions, and the thermal stability of the deposited alloy films under an annealing at 600…”

“…Because a layer of densely packed Pd nanoparticles (with a size of several nm) that had been prepared on the surface of Si substrates for catalyzing the subsequent EL Cu(Re) deposition 26,27 might also inhibit the Cu/Si interdiffusion, the EL Cu(Re) thus showed a better thermal stability than the EP Cu(Re) without the Pd layer did. Figure 6a plots the ESCA elemental concentration distributions (depth profiles) in a 400…”

Electroless Ni–Mo–P diffusion barriers with Pd-activated self-assembled monolayer on SiO2

“…A sputtered layer itself can also be employed as barrier layer [6][7][8][9][10][11][12][13][14][15]. However, sputtering procedure is usually conducted under high vacuum condition, and provides inherently poor step-coverage and discontinuities in the films at the sidewalls of fine holes [3].…”