A novel digital calibration scheme is developed to improve the linearity of a wide dynamic range (DR) CMOS imaging sensor, with a low calibration overhead. Experimental results show that the distortion of the fabricated imaging sensor reaches 275.6 dB over the 95.3 dB DR after calibration.Introduction: The dynamic range (DR) of CMOS imaging sensors is limited by the voltage space at the integration node. The DR can be nonlinearly expanded by scaling the integration time or the integration capacitance [1]. However, the imaging sensor's linearity is low from these wide DR schemes. Biomedical and scientific applications require imaging with high linearity [2]. The self-resetting pixel as shown in Fig. 1 can linearly expand the DR. The pixel resets itself when the integrated voltage V ph overflows the potential well V w (V rst 2 V ref ). The number of overflows (D w ) is recorded by a counter. The residual voltage (V r ) at the end of the integration is quantised by a column analogue-to-digital converter (ADC). If the comparator is ideal, the accumulated photo voltage can be readily calculated by
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