An Activity-Triggered 95.3 dB DR $-$75.6 dB THD CMOS Imaging Sensor With Digital Calibration

Yuan, Jie; Chan, Ho Yeung; Fung, S.; Liu, Bing

doi:10.1109/jssc.2009.2027929

Cited by 26 publications

(24 citation statements)

References 26 publications

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“…Both scenarios in Fig. 7(b) and (c) cause large in (6) and reduce the estimation accuracy. The code gap in Fig.…”

Section: B Signal Rangementioning

confidence: 99%

“…In this case, the second quantized code will be adopted. The code will be used in (6). This process will be performed with a sequence of for every MSB capacitor.…”

Section: Dithering Proceduresmentioning

confidence: 99%

“…The first decoder implements (6) in the calibration mode. As shown in (6), the correlation terms can separate into single-bit correlations in the MSB matrix and 5-b correlations of the LSB codes. These calculations need single-bit accumulators and 5-b adders with carry-in.…”

Section: E Digital Decodersmentioning

confidence: 99%

“…Moreover, the high-speed clock could couple to the analog sensor circuits [5]. Hence, more frequently, array sensors are organized in columns and quantized by ADC arrays ( [4], [6]- [11]). …”

mentioning

confidence: 99%

“…Single-slope ADCs are small in size. They are commonly used in slow array sensors with low-resolution data ( [4], [6], [7]). However, slope ADCs have high over-sampling clock ratio.…”

mentioning

confidence: 99%

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Digitally Calibrated 768-kS/s 10-b Minimum-Size SAR ADC Array With Dithering

Liu

Yuan

2012

IEEE J. Solid-State Circuits

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Array sensors require a high-performance analog-todigital converter (ADC) array with small area and low power. Successive-approximation register (SAR) ADC has good potential for ADC array due to its simple analog circuits. However, SAR ADCs with 10-b resolution and higher normally need a large capacitor array due to the stringent matching requirement. The large capacitor array also limits the ADC dynamic performance. The capacitor mismatch has been compensated by analog calibration techniques. In this work, a novel digital calibration method is developed for SAR ADC based on dithering. With dithering, weights of most significant bit (MSB) capacitors can be measured accurately so that very small capacitors can be used in the SAR ADC due to the relaxed matching requirement. A modified bit-cycling procedure is developed to avoid the code gaps caused by capacitor dithering. This calibration technique requires no analog calibration overhead and simple digital decoders. The technique is implemented in an ADC array design including 256 SAR ADCs for a high-speed CMOS imaging sensor in a 0.18-m CMOS process. The 10-b SAR ADC is designed with the minimum capacitor array size in the process. A single SAR ADC only occupies15 m 710 m. Sampling at 768 kS/s, peak DNL and peak INL of the original ADCs averaged across the array are 0.82 least significant bit (LSB) and 3.85 LSB, respectively. For a signal close to the Nyquist frequency, original ADCs have 7.96-b average ENOB. After calibration with dithering, ADCs have 0.55-LSB peak DNL and 0.77-LSB peak INL averaged across the array. The average ENOB improves to 9.83 b. Compared with the benchmark 10-b SAR ADCs, this design is the most area-efficient design. In this work, the calibration decoders are implemented off-chip. With a sample-and-hold amplifier, the calibration method can run in the background.Index Terms-ADC array, analog-to-digital converter (ADC), digital calibration, dithering, successive-approximation register (SAR).

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“…Both scenarios in Fig. 7(b) and (c) cause large in (6) and reduce the estimation accuracy. The code gap in Fig.…”

Section: B Signal Rangementioning

confidence: 99%

“…In this case, the second quantized code will be adopted. The code will be used in (6). This process will be performed with a sequence of for every MSB capacitor.…”

Section: Dithering Proceduresmentioning

confidence: 99%

Section: E Digital Decodersmentioning

confidence: 99%

mentioning

confidence: 99%

“…Single-slope ADCs are small in size. They are commonly used in slow array sensors with low-resolution data ( [4], [6], [7]). However, slope ADCs have high over-sampling clock ratio.…”

mentioning

confidence: 99%

See 3 more Smart Citations

Digitally Calibrated 768-kS/s 10-b Minimum-Size SAR ADC Array With Dithering

Liu

Yuan

2012

IEEE J. Solid-State Circuits

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A Biomimetic Frame-Free Event-Driven Image Sensor

Posch

2011

Focal-Plane Sensor-Processor Chips

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Optimized Hierarchical Cascaded Processing

Moons¹,

Bankman²,

Verhelst³

2018

Embedded Deep Learning

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Recently, there has been an increasing demand for advanced classification capabilities embedded on wearable battery constrained devices, such as smartphones or -watches. Achieving such functionality with a tight power and energy budget has proven a real challenge, specifically for large-scale Neural Network based applications. Previously, cascaded systems have been proposed to minimize energy consumption for such applications, either through using a single wake-up stage, or by using a linear-or tree based cascade of consecutive classifiers that allow early termination. In this work, we expand upon these concepts by generalizing cascades to hierarchical cascaded processing, where a hierarchy of increasingly complex classifiers, each designed and trained for a specific subtask is used. This hierarchical approach significantly outperforms the wake-up based approach by up to 2 orders of magnitude in energy consumption at iso-accuracy, specifically in systems with sparse input data such as speech recognition and visual object detection. This paper presents a general design framework for such systems and illustrates how to optimize them towards minimum energy consumption. The text further proposes a roofline model for cascaded systems, derives system level trade-offs and proves the approaches validity through a visual classification case-study.

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An Activity-Triggered 95.3 dB DR $-$75.6 dB THD CMOS Imaging Sensor With Digital Calibration

Cited by 26 publications

References 26 publications

Digitally Calibrated 768-kS/s 10-b Minimum-Size SAR ADC Array With Dithering

Digitally Calibrated 768-kS/s 10-b Minimum-Size SAR ADC Array With Dithering

A Biomimetic Frame-Free Event-Driven Image Sensor

Optimized Hierarchical Cascaded Processing

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