Completely vertical trench gate metal oxide semiconductor field-effect transistors (MOSFETs) have been produced using gallium nitride (GaN) for the first time. These MOSFETs exhibited enhancement-mode operation with a threshold voltage of 3.7 V and an on-resistance of 9.3 mΩ·cm2. The channel mobility was estimated to be 131 cm2/(V·s) when all the resistances except for that of the channel are considered. Such structures, which satisfy the key words “vertical”, “trench gate”, and “MOSFET”, will enable us to fabricate practical GaN-based power switching devices.

This paper presents two novel measurement methods to characterize silicon carbide (SiC) MOSFET devices. The resulting data are utilized to significantly improve the extraction of a custom device model that can now accurately reproduce device switching behavior. First, we consider the I d −V ds output characteristics of power devices such as SiC transistors. These are typically measured using traditional curve tracers, but the characterization of the high-voltage and high-current (HVHC) region is very challenging because of device power compliance and self-heating. In this paper, we introduce a measurement technique that overcomes self-heating and derives the HVHC region from switching waveforms. The switching transient characteristics of devices are used to determine drain current (I d ) as a function of drain-source voltage (V ds ) in the HVHC range. Second, we consider another challenging characterization area: measurement of nonlinear capacitances when device is turned on. These capacitance characteristics of on-state devices are important for correcting disagreements between simulations and measurements in turn-off switching transient waveforms and cannot be measured using a conventional capacitance-voltage meter. We introduce S-parameter measurements as an effective method to obtain the capacitance characteristics of both off-state devices and on-state devices. These novel measurement techniques have been applied to the modeling of a SiC device. The extracted device model, a modified version of the popular Angelov−GaN high-electron-mobility transistor model, shows significant improvement in terms of the accuracy of switching waveforms of devices over a wide range of operating conditions.

Enhancement-mode metal oxide semiconductor field effect transistors (MOSFETs) with trench gate structures have been developed. These MOSFETs show excellent DC characteristics with on-voltage of 5.1 V, i.e., enhancement-mode operation and extremely high channel mobilities of 133 cm 2 /(V s). This structure enables us to realize vertical switching devices with high breakdown voltage and highly integrated low on-resistance with the usage of excellent physical parameters of GaN. This excellent performance of these devices breaks though the realization of GaN-based power switching transistors.

SiC MOSFETs are applied to constitute a three-phase, 5-kW LLC series resonant dc/dc converter with isolation transformers. A switching frequency of around 200 kHz for the transistors successfully reduces the volume of these isolation transformers, whereas insulatedgate bipolar transistors (IGBTs) are not capable of achieving such a high switching speed. The high-voltage tolerance of SiC MOSFETs, 1200 V, enables increasing the input voltage up to 600 V. High-voltage tolerance, on the other hand, is not compatible with low on-resistance for Si MOSFETs. A three-phase circuit topology is used to achieve up to 5 kW of power capacity for the converter and reduce per-phase current at the same time. Currentbalancing transformers among these three phases effectively suppress a maximum peak current from arising in the circuit, a technique that miniaturizes the input and output capacitances. The conversion efficiency of the converter reaches 97.6% at 5-kW operation.

This paper focuses on revealing the mechanism of parasitic oscillation observed when SiC MOSFETs (metaloxide-semiconductor field-effect transistors) operate in halfbridge configuration. The relatively large parasitic feed-back capacitance (C gd ) of SiC MOSFETs, especially if the transistors have a low threshold voltage, enhances unintentional turn-on of the device, entailing parasitic oscillation in a half bridge circuit. The wide-band gap semiconductor power device should possess a structure of as low C gd as possible in addition to a device-specific circuit design, if the general advantage of wide band-gap power devices is utilized to facilitate high-speed switching. Keywords-Wide band-gap semiconductor transistor; High speed switching; Parasitic Oscillation; Half bridge circuit.High maximum electric-field strength signifies wide band-gap (WB) materials, typified by SiC and GaN, and thus a thin drift layer generally suffices to maintain the same withstanding voltage for WB based power devices compared to Si counterparts. This structure consequently produces a low on-state resistance which, in turn, allows smaller chips keeping the current tolerance of the devices [1].Miniaturization leads to small input capacitance (C gs ) facilitating high-speed switching, whereas thin drift layers and high carrier concentration cause large gate-drain capacitance (C gd ). Our team has found that relatively large C gd enhances the possibility of parasitic oscillation in a half bridge (HB) configuration as depicted in Fig.1, and revealed that the unintentional turn-on [2] of the high-side FET (HS) triggered the oscillation. This oscillation is similar to the oscillation described in [3] and [4]. Subscript symbols in this paper and parameters used in simulation are listed in Table 1.We investigated the mechanism of this parasitic oscillation in the HB circuit as shown in Fig.1. The gate driver drove the low-side FET (LS) applying +18 V pulses, and the HS worked as the freewheeling device because of its shorted gate-source.After V gs,L goes up to +18V, V gs,H = 0 V, V ds,L = 0 V, and V ds,H = E, ideally. Experimental waveforms in Fig.2, however, show unexpected oscillations.HS and LS periodically forms a short circuit, indicated by the experimental fact that I d,L and I d,H swings in antiphase with the almost same absolute value, and thereby dI d,L /dt gives L s to be 67nH. Conventional impedance measurement estimated L s to be about 60nH. L g is the parasitic inductance in the shorted line between gate and source of HS. In this experiment, the gate-source short line of HS is long enough to differentiate between resonance frequency in the gate-source circuit and the power circuit including two FETs and E. This line inductance is estimated about 600nH by impedance measurement.gs Low Side L Resistor R 67nH L s 100V E High Side H Capacitor C source s Inductor L drain d Current I gate g Voltage V 20pF (V ds =1200V) C gd 1.25nF (V ds =0V) C gd 18V/0V V gs 600nH L g 0.65nF C gs Low Side L Resistor R 67nH L s 100V E High Side H Capacito...